內插式可變區間之超取樣資料與時脈回復電路

A Variable-Interval Oversampling Clock and Data Recovery Circuit Using Interpolation

江昱興(Yu-Hsing Chiang)

指導教授 ： 曹恆偉

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2009年)

https://doi.org/10.6342/NTU.2009.01254

摘要

資料與時脈回復電路是接收機的一部分，且在一個通訊系統中扮演很重要的角色。由於傳輸通道的頻寬是有限的，嚴重的抖動因此產生。一個有高抖動容忍的資料與時脈回復電路可以提供高準確性的資料，但大抖動與不對稱的抖動會降低其容忍度。使用超取樣時脈的資料與時脈回復電路可以減緩以上所提的問題，產生較佳的抖動容忍度與較低的錯誤位元率。
　　幾分之一速率的超取樣的資料與時脈電路被應用在考量速度和雜訊容忍度。一個四分之一的三倍超取樣資料與時脈電路被提出，它的超取樣時脈之間的距離會根據輸入的資料眼圖而變。結果，此資料與時脈回復電路的抖動容忍度比固定取樣時脈之間距離的資料與時脈回復電路的好。此篇論文提出一個時脈產生的改良方法，其好處有：減輕電壓控制振盪器的延遲單元級數限制，最大的抖動量限制，以及延遲單元使用種類限制。此資料與時脈回復電路設計在0.18微米的互補式半氧電晶體的製程下，目標是符合光纖通道的規範。當資料速率為5千兆位元，模擬的資料峰對峰值抖動為22微微米。當資料速率為4.25千兆位元，量測的資料峰對峰值與資料均方根值抖動分別為76.67微微米與9.07微微米。此晶片耗掉0.74*0.84微米平方的面積，量測時消耗大約170毫瓦的功率，包含輸出級。

關鍵字

可變區間 ； 超取樣 ； 資料與時脈回復 ； 內插

並列摘要

A clock and data recovery circuit (CDR), which is a part of a receiver, plays an important role in a communication system. Since bandwidth of transmission channels is limited, severe jitter is produced. A CDR with higher jitter tolerance provides higher-accuracy data, but large magnitude of jitter and asymmetry of jitter reduce jitter tolerance. Using oversampling clocks for CDR alleviates the problem mentioned above, resulting in enhanced jitter tolerance and lower BER.
A fractioned-rate oversampling CDR is applied in consideration of speed and jitter tolerance. A quarter-rate 3x-oversampling CDR was proposed, where the Intervals between the edge-sampling clocks and decision clocks are variable according to incoming data eye diagram. As a result, the CDR’s jitter tolerance is better than a fixed-interval CDR’s one. The thesis proposed a modified method of clock generation whose advantages are relieving the restriction of the number stage of delay cells, a limitation of the maximum magnitude and the restriction of types of delay cells. The CDR is designed in 0.18-μm CMOS technology and targeted to fit the specification of fibre channel. The simulated peak-to-peak data jitter is 22-ps at data rate of 5-Gbps, the measured peak-to-peak and RMS jitter are 76.67-ps and 9.07-ps, respectively, at data of 4.25-Gbps. The chip size is 0.74*0.84-mm2, and the measured power consumption is about 170-mW including output buffers.

並列關鍵字

Variable Interval ； Oversampling ； Clock and Data Recovery ； Interpolation

參考文獻

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