透過您的圖書館登入
IP:18.222.68.81
  • 學位論文

利用模擬系統進行效能與能耗剖析

Performance and Power Profiling with Emulated Systems

指導教授 : 洪士灝

摘要


模擬是一種常見用來協助系統設計與最佳化的方法。對於系統層級的最佳化而言,能耗與計算資源的多寡是兩個最重要的限制。為了精確的對系統效能與能耗進行預測,我們必須針對每個硬體元件可能運行的狀態,分別建造能耗與時間模型。此外,在一個真實的模擬環境中,追蹤軟體的執行與硬體使用狀況並適時的模擬輸入輸出系統,則是能夠準確進行預測的關鍵。然而,傳統模擬的方式在實際執行上會有相當的困難。首先,要對一個複雜的系統,建構一個週期精確的模擬環境並不是一件簡單的事情。特別是要開發一個異質多核心的模擬系統的時候。再者,對於I/O頻繁的應用程式,速度較慢的模擬環境會大幅的改變程式行為與效能數據。最後,傳`統的軟體效能剖析工具並沒有辦法在模擬器上面運作。在此情況下,要對複雜的軟體,如:Java應用程式,進行效能分析時會有相當的困難。 本篇論文提出了一個虛擬效能分析的架構(Virtual Performance Analyzer Framework)來解決上述的問題。此架構利用一般仿真器並在其中加入效能與能耗模型,來降低建構一個模擬環境所需的時間。我們提供多種效能與能耗模型,來幫助使用者了解仿真器模擬的速度對軟體行為是否會產生影響。此外,我們提出了一個利用仿真器來建構剖析工具的方法。此方法藉由在仿真器中加入效能與能耗監控的裝置與軟體行為分析器,。另一方面,我們擴展VPA的架構,並利用現有的仿真器來快速建構異質多核心系統的模擬環境。我們加入時間同步的機制與競爭模型(contention model)以正確的估計系統效能。我們已經將此架構實作,並且使用真實的應用程式作為個案研究來展示此架構的實用性。

並列摘要


Simulation is a common approach for assisting system design and optimization. For system-wide optimization, energy and computational resources are often the two most critical limitations. Modeling energy-states of each hardware component and time spent in each state is needed for accurate energy and performance prediction. Tracking software execution and hardware utilization in a realistic operating environment with properly modeled input/output is key to accurate prediction. However, the conventional approaches can have difficulties in practice. First, for a complex system, building a cycle-accurate simulation environment is no easy task. This is especially true for a multicore system consisting of different types of processing cores. Secondly, for I/O-intensive applications, a slow simulation would significantly alter the application behavior and change its performance profile. Thirdly, conventional software profiling tools generally do not work on simulators, which makes it difficult for performance analysis of complicated software, e.g., Java applications. This dissertation presents a virtual performance analysis framework (VPA) to tackle the above problems. The proposed framework eases the effort of building a simulation environment by leveraging the infrastructure of functional emulators and adding performance and power models. Multiple sets of the performance and power models can be selectively used to verify if the speed of the simulated system impacts the software behavior. Furthermore, we develop the methodology to build profiling tools with the functional emulator by adding performance/power monitoring facilities and the software activity analyzer. In addition, we extend the VPA framework to facilitate the construction of an emulation environment for a heterogeneous multicore system via integrating the existing processor emulators. The timing synchronization mechanism and the contention model are also included to give an accurate estimate of system performance. We have prototyped the framework and our case studies of real life applications show that the information provided by our tools are useful for software optimization and system design for complex systems, such as Android smartphones.

參考文獻


[2] DTrace: Dynamic tracing in the solaris operating system. http://opensolaris.org/os/community/dtrace/.
[6] Lars Albertsson. Holistic debugging – Enabling instruction set simulation for software quality assurance. In MASCOTS 2006, pages 96 – 103, sept. 2006.
[9] Rajeshwari Banakar, Stefan Steinke, Bo-Sik Lee, M. Balakrishnan, and Peter Marwedel. Scratchpad memory: design alternative for cache on-chip memory in embedded systems. In CODES, pages 73–78, 2002.
[14] Geoffrey Blake, Ronald Dreslinski, and Trevor Mudge. A survey of multicore processors. IEEE Signal Processing Magazine, 26(6):26–37, 2009.
[16] David Brooks, Vivek Tiwari, and Margaret Martonosi. Wattch: A framework for architectural-level power analysis and optimizations. In ISCA, pages 83–94, 2000.

延伸閱讀