雙相位七位元數位控制脈波寬度調變器

Dual Phase 7-bit Digital-Controlled Pulse Width Modulator

葉建祖(Jian-Tzu Yeh)

指導教授 ： 陳怡然

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2020年)

https://doi.org/10.6342/NTU202004263

摘要

科技日新月異，未來人類生活將往智慧顯示的方向發展，利用無線傳輸顯示資料為智慧顯示的重點，隨著科技對資料頻寬的要求逐漸倍增，採用傳統直接轉換發射機(Direct Conversion Transmitter)使很多類比元件已無法滿足高頻寬傳輸時所需的線性度，例如: 數位類比轉換器的高精度要求、混頻器及功率放大器必須足夠線性等，因此許多研究開始朝向數位化的方式來設計射頻發射機，近年被提出的脈衝調變極座標發射機(Pulse-Modulated Polar Transmitter, PMPT)為傳送資料之發射端，有別於傳統直接轉換發射機，將傳送資料的基頻複數訊號轉為振福及相位，且振幅大小利用脈衝寬度調變技術(Pulse Width Modulation)使輸出波形的振幅僅有0或1的兩種可能，如此一來便可使用更不線性的功率放大器來提升傳輸效率，本論文設計之雙相位中心式數位脈波寬度調變器將用來控制射頻脈衝調變器，可應用於現今已成熟的長期演進技術(LTE)，或正在發展中是未來趨勢的新無線電(NR)，高頻率、高解析度和高精度的脈波輸出，將有效提升應用於射頻脈衝調變器的表現。
本論文使用TSMC 0.18-μm CMOS製程實現，晶片面積為0.96 × 0.75 mm2，規格為輸出相位差異180度的七位元100MHz中心式數位脈波寬度，更準確地描述晶片功能為數位─脈波寬度轉換器，輸入七位元的數位訊號，輸出對應的脈波寬度(工作週期)，量測之DNL介於 ± 0.3 LSB，INL介於 - 0.5 LSB ~ + 0.6 LSB，總功耗為14.4 mW，可量測之輸出脈寬範圍為2.5% ~ 96.3%。

關鍵字

數位脈波寬度調變器 ； 射頻脈衝調變器 ； 開關鍵控調變 ； 振幅偏移調變 ； 脈衝調變極座標發射機

並列摘要

With the rapid development of science and technology, the life in human society will move in the direction of smart display. Higher bandwidth is required for wireless transmission nowadays. The use of traditional direct conversion transmitter with analog components, such as: ultra-high precision of digital-to-analog converter, and sufficient linear properties of the mixer and power amplifier, will no longer satisfy the required linearity of high-bandwidth transmission. Therefore, many studies have begun to design digital RF transmitter. The Pulse-Modulated Polar Transmitter (PMPT) proposed in recent years, is a TX for wireless transmission, in which unlike conventional direct conversion transmitters, the data of baseband complex signal is converted to magnitude and phase. The pulse width modulation approach is utilized to allow the amplitude of the output waveform alternating between two states, 0 or 1. Thus, it becomes possible to use non-linear power amplifier to boost the transmission efficiency. The DPWM designed in this thesis would be used to control the RF Pulse Modulator, which could be used in the 4GLTE or 5GNR PMPTs.
The chip is fabricated in a 0.18-μm CMOS process, and its size is 0.96 × 0.75 mm2. The chip generates the output of dual phase 7-bit 100MHz center-aligned digital pulse width, i.e. digital to pulse width converter. The input is digital code, and the output is pulse width. The digital code is mapped to the corresponding pulse width. Measured DNL is between -0.3 LSB and +0.3 LSB, and INL is between -0.5 LSB and +0.6LSB. The total power consumption is 14.4 mW. The measureable output duty cycle is between 2.5% and 96.3%.

並列關鍵字

Digital Pulse Width Modulator ； RF Pulse Modulator ； On-Off Keying Modulation ； Pulse-Modulated Polar Transmitter

參考文獻

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