正規輔助多重邊界案例與多重操作模式之時序分析與最佳化技術

Formal-Assisted Multi-Corner Multi-Mode Timing Analysis and Optimization Techniques

蔡詩蘅(Shih-Heng Tsai)

指導教授 ： 黃鐘揚

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2012年)

https://doi.org/10.6342/NTU.2012.01618

摘要

電路設計中的時序收斂已經成為現代超大型積體電路設計流程中的最大瓶頸。為了確保電路能夠有效及正確的運作，嚴密精確的時序分析及強效有力的時序佳化兩者不可或缺。
傳統的時序分析方法可以分為靜態時序分析(STA)以及動態時序分析(DTA)。靜態時序分析可以看作為一個電路延遲上限的傳遞運算過程，也就是將電路中每個節點在最差的情況下的延遲計算出來。而動態時序分析則是考慮在給定的輸入信號、波形之下，模擬在一段給定時間之內電路整體的信號行為，此種模擬雖然精確，但較靜態時序分析來得耗時許多。在過去晶片設計及半導體產業急速發展的數十年間，傳統的靜態時序分析往往作為一快速並有效的時序檢驗工具來計算電路的延遲，其快速的原因在於忽略了許多信號之間的交互作用如錯誤路徑(false paths)以及多重信號轉換(multiple input transition)等等。然而，現今晶片設計已走進奈米時代，時序分析需要更高的精密度以及正確性，因此信號的交互影響必須納入考慮。
除此之外，奈米時代所帶來在時序驗證上的挑戰還包括了各種製程上的不確定性，而必須考慮各種電路環境或製程參數的極限值，或稱為多重邊界(multiple corners)，以及低功率導向的設計需求所帶來的多重功率模式(multiple modes)，其中各模式往往有著不同的輸入電壓或時脈操作頻率。這類現代晶片設計上必須考慮的多重場景(multiple scenarios)，或統稱為 multi-corner multi-mode (MCMM)，已經大幅提升了不管是時序分析或是時序最佳化的複雜度。傳統時序分析往往同時考慮一個或兩個設計場景，而在面臨MCMM的問題時需要反覆執行相當大量的計算次數，導致一次全電路MCMM時序分析就非常耗時。更甚，在考慮MCMM時，傳統的時序最佳化方法，例如處理緩衝器置入(buffer insertion)的問題時非常有效的動態規劃法，無法同時考慮多重設計場。因此，電路設計者必須每次針對單一模式或角落作最佳化，反覆此過程以修正在各模式或角落的時序錯誤。這樣的手動設計過程往往極為耗時，並有可能造成設計上無法收斂，或是將時序設計上的限制過度保守化來避免錯誤，從而造成整體設計上的困難以及效能的降低。簡言之，MCMM的時序設計限制大幅縮減了晶片設計上容錯的空間以及降低了晶片的良率。
在本論文中，我們提出了一個整合性的正規輔助時序分析暨最佳化設計流程來解決MCMM的設計難題，並且增進了時序驗證方法的性能。此整體驗證流程包含了三大主要部份，首先是一統合性MCMM 靜態時序分析器 (MCMM-STA) 以同時計算在不同的設計場景下的電路延遲；再來是一正規輔助之時序分析方法 (FATA) ，用以判斷由傳統 STA 或是 MCMM-STA 所計算出之各時序關鍵路徑 (timing critical path) 是否為錯誤路徑 (false path)，同時考慮多重輸入信號變化以計算更精確的延遲上限；第三為一新穎的半正規緩衝器置入演算法，其可在 MCMM-STA 及 FATA 之基礎上設計用以計算最低成本並符合 MCMM 時序要求之緩衝器配置。

關鍵字

時序分析 ； 時序最佳化 ； 正規方法 ； 多重邊界案例

並列摘要

Timing closure has always been the biggest bottleneck in the modern VLSI design flow. To assure the correctness of circuit timing behavior, both rigorous timing analysis and powerful timing optimization are required.
Traditional timing analysis techniques include static timing analysis (STA) and dynamic timing analysis (DTA). STA can be considered as a delay upper bound propagation process which simply takes the maximum delay at every circuit node, while DTA requires the input signal information (pattern) and simulate the circuit timing behaviors in a given time period with much larger run time. In the past decades, traditional STA has been a fast and decent tool to compute delay upper bound by ignoring signal interactions such as false paths and multiple input transitions. However, to achieve higher accuracy which is needed in modern design scale, such interactions must be taken into consideration.
In addition, recent challenges on timing verification come from the unpredictability due to process variations (multiple corners) and the demand for low power design methodologies (multiple power modes with multiple supply voltages and operating frequencies). These multiple design scenarios, so called multi-corner multi-mode (MCMM), have significantly increased the complexities of both timing analysis and optimization. Traditional timing analysis techniques usually handle one or two scenarios at a time and require a great amount of iterations and run time to complete full circuit MCMM timing analysis. Moreover, traditional timing optimization approaches, such as dynamic-programming-based buffer insertion techniques, are unable to handle MCMM simultaneously. As a result, we need to either iteratively optimize the design one mode/corner at a time, leading to the timing convergence problem, or take a conservative approach in defining the timing constraints that ends up unsatisfiable for the original design specification. In short, MCMM timing constraints would attenuate the design margin and greatly reduce the yield.
In this dissertation, we propose an integrated formal-assisted timing analysis and optimization flow which solves the MCMM issues and increases the capability of the timing verification techniques. The overall verification flow includes three parts: First, a unified Multi-Corner Multi-Mode Static Timing Analyzer (MCMM-STA) is proposed to efficiently compute the worst-case delay among various process corners; Second, a Formal-Assisted Timing Analysis (FATA) technique is applied to formally detect false paths identified by our MCMM-STA engine, consider multiple-input transitioning effects in delay calculations, and generate input transition patterns for true critical paths in timing debugging and post-layout simulations; And third, a novel Semi-Formal Buffer Insertion (SFBR) algorithm is devised to compute a minimum-cost buffer placement for the MCMM timing constraints based on the results of our MCMM-STA and FATA.

並列關鍵字

Timing Analysis ； Timing Optimization ； Formal Methods ； Multi-corner Multi-mode

參考文獻

[1] S. Borkar, T. Karnik, and Vivek De, “Design and reliability challenges in nanometer technologies,” in Proceedings of Design Automation Conference, 2004, pp. 75-75.

[3] D. Blaauw, K. Chopra, A. Srivastava, and L. Scheffer, “Statistical Timing Analysis: From Basic Principles to State of the Art,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, pp. 589-607, April 2008.

[4] A. Mutlu and M. Rahman, “Statistical methods for the estimation of process variation effects on circuit operation,” IEEE Transactions on Electronics Packaging Manufacturing, vol. 28, pp. 364-375, Oct. 2005.

[5] Lin Xie, A. Davoodi, Jun Zhang, and Tai-Hsuan Wu, “Adjustment-based modeling for Statistical Static Timing Analysis with high dimension of variability,” in Proceedings of International Conference on Computer-Aided Design, 2008, pp. 181-184.

[6] S. Onaissi and F. Najm, “A Linear-Time Approach for Static Timing Analysis Covering All Process Corners,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, pp. 1291-1304, July, 2008.