- 學位論文
階層式微顯影光源光罩最佳化演算法使用Abbe-PCA
Micro-lithography Hierarchical Source and Mask Optimization using Abbe-PCA
摘要
隨著超大型積體電路(VLSI, very-large-scale integrated-circuit)製程技術的演進，元件的特徵尺寸(feature size)正挑戰微顯影成像系統(micro-lithography image system)的解析極限，使得成像結果因繞射效應明顯地偏離了原本的設計圖樣(design pattern)。 為此，各種解析度增強技術(RET, resolution enhancement technology)廣泛地被提出，以期盡可能彌補設計圖樣和成像結果之間的差距，進而維持先進積體電路的量產良率與功能正確性。幾種代表性的技術諸如相移光罩(PSM, phase shift mask)、偏軸照明(OAI, off-axis illumination)以及光學鄰近修正術(OPC, optical proximity correction)等均有助於成像結果的改善。 其中，光學鄰近修正術考慮微顯影系統的行為，並對光罩圖樣(mask pattern)進行最佳化修正，以期能抵消微顯影系統的作用而得到原本的設計圖樣，但仍受限於光罩的製造可行性和成本而無法達到理想的結果。 於本論文中，我們考慮最新的光源光罩最佳化技術(SMO, source mask optimization)，試圖將曝光光源的組態也納入考慮以增加解空間大小。亦即針對每個電路的設計圖樣進行偏軸照明的最佳化，比起傳統只修正光罩的方法有更大的彈性，而能更貼近理想的成像結果。 然而，如果要得到較佳的結果，往往需要考慮越多最佳化變量；反之，若在低解析度情況下模擬，較少的變量則有助於模擬速度。於本論文中，我們嘗試階層式的光源光罩最佳化，亦即在低解析度快速得到一初步結果，再以高低解析度得到更進一步的精確解，而能兼顧低解析度的速度和高解析度的精度。 此外，為了評估最佳化組態是否有效改善成像結果，每次改變光源或光罩時都需要對最佳化組態頻繁地進行模擬。而在現今元件數以百萬計的電路設計中，此一龐大的模擬計算往往耗日費時，因此如何快速得到成像結果的高速微顯影模擬器也佔有相當重要的地位。 於本論文中，我們使用阿貝主成份分析(Abbe-PCA, Abbe principal component analysis)對最佳化過程中產生的摺積成像核心(convolution image kernel)進行快速壓縮。並利用摺積查表(convolution lookup table)加速，僅針對取樣觀察點(sampled observation)的成像強度誤差(IIE, image intensity error)作為最佳化過程中的目標函數(objective cost function)，來取代傳統需要費時全光罩模擬的邊緣放置誤差(EPE, edge placement error)。
並列摘要
As the VLSI manufacture technology develops, the feature size of micro-electronic devices shrinks smaller than the wavelength of exposure light source and challenging the limit of micro-lithography image system. Consequently, optical diffraction significantly deviate the exposed image result from the original design pattern we expected. Therefore, lots of resolution enhancement technologies (RETs) are so far widely proposed to minimize the difference between design pattern and image result. Conventional RETs such as phase shift mask (PSM), off-axis illumination (OAI), and optical proximity correction (OPC) are in favour of improving the printing quality. The OPC method tried to take the behaviour of micro-lithography image system into consideration when optimizing the mask pattern with pre-correction. The mask pattern after correction is aimed to cancel non-ideal effects of micro-lithography process and have expect image result returned. However, the image quality using simply OPC is still not perfect due to limits such as mask cost and manufacturability. In this work, we consider the latest method of source mask optimization (SMO), which take not only shapes on mask pattern but also the configuration of illuminator into consideration in broadening the solution space. In other words, the light source and mask are optimized simultaneously for an individual design given, which could provide finer image result and more flexibility using combined RETs than using simply conventional ones. However, a detailed optimization may involve more variables, which cause a better result but costs longer runtime. In the other hand, a rough optimization in low resolution may involve fewer variables with shorter runtime but worse result. In this work, we propose to perform the source mask optimization in a hierarchical way, which could take both the advantage of faster runtime in lower resolution and detailed refinement in higher resolution. Besides, micro-lithography image simulation is performed repetitively each time we change the source or mask to have a cost function evaluated in determining whether the image result is enhanced during optimization. Therefore, high speed micro-lithography simulator is in strong demand for growing computational complexity to state-of-art RETs when handling modern industrial cases with millions of devices. In this work, we utilize the principal component analysis on Abbe’s image formulation (Abbe-PCA) for high speed kernel compaction on the point spread functions produced during source optimization. Also, convolution lookup table is introduced to accelerate cost function evaluation defined using image intensity error (IIE) on sampled observation points instead of traditional edge placement error (EPE), which demands a time consuming full image simulation.
參考文獻
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