電子構裝區域排列式垂直互聯結構之訊號完整度電氣模型化與設計

Electrical Modeling and Design for Signal Integrity of Area-Array Vertical Interconnects in Electronic Packaging

孫瑞伯(Ruey-Bo Sun)

指導教授 ： 吳瑞北

國立臺灣大學/電機資訊學院/電信工程學研究所/博士(2011年)

https://doi.org/10.6342/NTU.2011.01572

摘要

為了最佳化電子構裝的電氣效能，垂直互聯結構的電氣模型化與訊號完整度設計是相當關鍵的議題。本論文探討於區域排列垂直互聯結構的各種重要雜訊類型，包含反射與串音、同步切換雜訊以及基板損耗，分別以三種不同型態的垂直互聯結構：針腳(彈簧針)，球狀(凸塊、錫球)，連通柱(直貫矽晶連通柱)為實例，進行分析與模型化，並提出一系列的系統化設計方法。
於同步切換雜訊的分析與抑制方面，本論文以一個凸塊陣列為例，提出一個利用基因演算法之系統化設計方法以獲得最小同步切換雜訊所對應的最佳訊號接地擺置。為了降低計算複雜度，亦開發了一個新的電路簡化方法，將一個包含構裝線及凸塊陣列的完整輸出入緩衝器電路簡化至只含電感與等效電流源的電路，並推導其理論的適用範圍。由最佳化的結果能夠得知最佳的訊號接地比、相對應的接地擺置並歸納出設計的準則。
於訊號反射與串音雜訊的抑制方面，對於各種不同訊號接地擺置的阻抗匹配與串音設計是一個重大的挑戰。本論文以一個彈簧針陣列為例，考量各種不同的針腳擺置，提出一個新穎的折衷阻抗匹配設計方法，以獲得對於所有針腳擺置均符合反射損耗規範的彈簧針尺寸範圍以及操作頻率上限。新方法包含了兩種設計圖表：(1) 彈簧針等效阻抗對半徑間距比的設計圖表與 (2) 反射係數對電氣長度與相對阻抗差的設計圖表，利用設計圖表能夠快速地達成設計目標。為了降低串音雜訊，本論文提出一個直接整合於測試插槽中的新型隔離結構。利用全波與準靜態方法能夠設計隔離結構的尺寸使得所有訊號接地擺置的反射與串音雜訊由直流至10 GHz均小於-20 dB。此外利用新型測試夾具量測得到的S參數結果與設計結果想當吻合，因此驗證了分析方法與設計概念的正確性。
於傳輸線基板損耗所造成色散雜訊的抑制方面，等化器技術能夠用於補償損耗效應。本論文以直貫矽晶連通柱為例，提出一個能夠完美補償直貫矽晶連通柱的損耗並且僅由一對並聯電阻電容所構成的新型被動等化器。首先推導直貫矽晶連通柱的解析等效電路模型，並驗證其正確性至20 GHz。基於解析電路模型，一個創新的重要性分析被用來檢視各個電路元件彼此間的相對重要性，進而得到一個相當簡化的電容電導電路模型，並由此推導出等化器的理論與設計公式。多層堆疊的矽晶連通柱在串接所設計的等化器之後，輸出端眼圖的時脈抖動幾乎等於零，也幾乎完全張開。

關鍵字

訊號完整度 ； 垂直互聯結構 ； 電子構裝 ； 同步切換雜訊 ； 凸塊/錫球擺置 ； 最佳化 ； 折衷阻抗匹配設計 ； 彈簧針 ； 測試插槽 ； 自動測試設備 ； 反射損耗 ； 串音雜訊 ； 等化器 ； 損耗補償 ； 直通矽晶連通住

並列摘要

In order to optimize the electrical performance of electronic packaging, the electrical modeling and designs for signal integrity (SI) of vertical interconnects are the considerably critical issues. In this dissertation, the various significant kinds of noises, including reflection, crosstalk, simultaneous switching noise (SSN), and substrate loss in the area-array vertical interconnects, are investigated by taking three different types of vertical interconnects, consisting of pin type (pogo pin), ball-shape type (bump and solder ball), and via type (through silicon via, TSV) as examples. A series of novel and systematic methodologies are proposed for the investigations and noise suppression.
With regard to the analysis and suppression of SSN, this dissertation takes a bump grid array as an example to propose a systematic design methodology, acquiring the optimal signal-ground assignment with the minimized loop SSN by using genetic algorithm (GA). For the reduction of computing complexity, a new circuit simplification method is developed to simplify a complete I/O buffer circuits, including package traces and a bump array, into a circuit of inductors and current sources together with its applicable range derived analytically. Based on the optimized results, the optimal signal-to-ground ratio and its associated bump assignments are obtained. Also, some heuristic designs are proposed, accordingly.
As for suppressions of the reflection and crosstalk, designs of the impedance match and crosstalk reduction for all possible signal-ground assignments are very challenging. In this dissertation, a novel compromise impedance match design is proposed for a pogo pin array with the diverse pin assignments to find the permissible window of the pogo pin geometries and the upper bound of operating frequency such that all pin patterns meet the specification on return loss. Two different types of design charts are developed to greatly facilitate the design. The first one is the equivalent impedance of pogo pin versus the pin radius-to-pitch ratio. The second one is a much general chart in terms of the reflection coefficient versus the electrical length and the relative impedance difference of the pogo pin. On the other hand, for the sake of the crosstalk reduction in the pogo pin array, a new isolation structure directly integrated in a test socket is proposed. The isolation structure is appropriately designed by adopting the full-wave and quasi-static methods so that the reflection and crosstalk for all pin patterns are both smaller than -20 dB over dc to 10 GHz. The measured S parameters obtained by using the new test fixtures have good correlations with simulated ones, validating the proposed ideas and methodologies.
Regarding to the suppression of dispersion noise due to the substrate loss, the equalization technique can be introduced to compensate the lossy effect. Considering the TSV interconnect in the three-dimensional integrated circuit (3D IC), a novel passive equalizer capable of the perfect compensation for lossy effects of TSV is devised. It is only composed of a parallel resistance-capacitance (RC) circuit. To design the equalizer, the analytic circuit model of TSV is derived and substantiated up to 20 GHz, and based on which, the novel significance analysis is implemented to inspect the relative importance of each parasitic element, thereby attaining a much simplified capacitance-conductance (CG) circuit model. It proves that the first order effects of TSV are attributed to the oxide liner and the lossy silicon substrate. The design theory and formulas of the equalizer can also be derived accordingly. The output eye diagram of multi-stacked TSVs in series with the designed equalizer is nearly open with zero timing jitter.

並列關鍵字

Signal integrity ； vertical interconnect ； electronic packaging ； Simultaneous switching noise ； bump/ball assignment ； bump/ball map ； optimization ； compromise impedance match ； pogo pin ； test socket ； automatic test equipment ； return loss ； crosstalk ； equalizer ； loss compensation ； through silicon via

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