批次式蝕刻於矽晶圓薄化製程技術之研究

A Study on Batch Etching Process for Wafer Thinning

詹景棓(Jing-Pou Zhan)

指導教授 ： 楊宏智

國立臺灣大學/工學院/機械工程學研究所/碩士(2007年)

https://doi.org/10.6342/NTU.2007.00899

摘要

矽晶圓薄化為現今必然之趨勢，目前最廣為運用的技術是採用輪磨進行薄化作業， TTV 佳、生產速度快為其優點；但輪磨以機械力進行材料移除，加工過程必然產生次表面破壞層 ( SSD ) 以及殘留應力。當矽晶圓厚度較大時，其本身強度足夠則次表面破壞層影響有限，但是當進行矽晶圓薄化時，由於矽晶圓變薄後支撐力下降，輪磨後的殘留應力將造成矽晶圓的彎曲甚至捲曲，使後續的加工作業更加困難，而次表面破壞層亦會使變薄的矽晶圓更加的脆弱。輪磨矽晶圓厚度至 200μm 左右， Warp 問題即開始被突顯；以輪磨繼續進行薄化時，勢必會因殘留應力遭遇極限。
本研究建立在現行輪磨可達到的薄化基礎上，以批次式蝕刻方式將矽晶圓做更進一步的薄化。過去矽晶圓薄化製程輪磨後也會進行批次蝕刻的動作，但主要作用是產生後續覆層作業所需表面或是去除殘留應力消除 Warp 的作用，而非移除矽晶圓材料進行薄化作業，通常蝕刻量很低只有數μm。本研究以蝕刻 50μ 為目標，一方面以化學蝕刻進行進一步薄化，同時達到消除殘留應力的需求。
本研究先以小試片初步找出製程參數，再配合田口實驗了解各製程參數影響、系統特性以及找出最佳製程參數，利用現有蝕刻設備做有效調整。規劃上首先嘗試以製作 100μm 矽晶圓為目標，圓滿達成後再更進一步挑戰蝕刻薄化極限。
當矽晶圓厚度低於200μm後，本身強度不足常造成後續作業困擾，無論是泡酸、水洗、旋乾或是攜帶的過程都很容易造成破片。因此本研究另設計出以真空吸附方式，將薄化矽晶圓吸附於耐酸治具上，利用治具為基底支撐薄化矽晶圓，使後續泡酸作業不會破裂損毀，讓批次式蝕刻得以實現。

關鍵字

矽晶圓 ； 薄化 ； 濕式蝕刻 ； 批次式蝕刻 ； 真空治具

並列摘要

Thin Wafer is becoming the main stream in the semi-conductor industry. The most widely used technology is grinding process; the advantage of the process is better TTV values and faster production. On the other hand, the disadvantage of the process is that grinding requires mechanical method to remove the material, which means during the process it will grow a sub-surface damage (SSD) layer and residual stress. It gives more trouble for the post-decomposition process. SSD will also cause the wafer to be feebler and easily to break. When the wafer grind to 200 μm, Warp starts to become an issue; If applying the grinding process to further thin the wafer, the residual stress will meet its limit.
This research is base on the recent technology of grinding process, and then apply the batch etching method to improve the wafer thining. In the past, after the wafer grinding process, a batch etching was still applied. But its main purpose was to remove a layer with the residual stress of warp. This etching process was not used to thin the wafer; usually it only etched a few μm. This research is targeting a 50 μm etched on the wafer. First of all, applying the chemical etching method to improve the thinning process and also achieve the purpose of removing residual stress.
This research cuts the wafer into small piece of chips and then gives different treatment on the chips to figure out the process parameters. Taguchi Method was applied to explore the process parameters, system characteristics, and find out the best process parameters. Using the recent etch equipment to make effective adjustment, in the design phase, the primary target was to achieve a 100 μm thin wafer. Once it is successfully achieved, the next challenge would be the limitation of etching process.
When the wafer thickness is lower than 200 μm, usually its interior strength would not be able to support itself through the post-decomposition process. No matter it is etching in acid, cleaning by water, drying by spin, or carrying, it is easily to cause fractal on wafer. There for, this research specifically designs a vacuum chuck to hold the thin wafer on the acid-prof jig. Use the jig to support the thin wafer, so it would not break during the post-deposition process. This auxiliary device ultimately achieve the batch etching process.

並列關鍵字

Silicon Wafer ； Thinning ； Wet Chemical Etching ； Batch Etching ； Vacuum Jig

參考文獻

[21]廖錫田，”矽晶圓薄化技術之研究”，國立台灣大學碩士論文，2005

[3]T. G. Bifano, T. A. Dow, and R. O. Scattergood, “Ductile Regime Grinding : A New Technology for Machinning Brittle Materials”, Journal of Engineering for Industry, Transactins of the ASME, Vol.113, pp.184-189, 1991.

[5]Marco Steinert, etc. “Reactive Species Generated during Wet Chemical Etching of Silicon in HF/HNO3 Mixtures”, J. Phys. Chem. B, Vol. 110, No. 23, 2006

[10]Wing C. Hui, “How to prevent a runaway chemical reaction in the isotropic etching of silicon with HF/HNO3/CH3COOH or HNA solution“, The International Society for Optical Engineering, Vol. 5276, pp. 270-279, 2004

[12]Bagriy and O. Siniaguine, “Characterization of Deep Si Etch Profiles Formed by Atmospheric Downstream Plasma”, The International Society for Optical Engineering, v 4174, p 111-118, 2000