應用於超寬頻及高速有線接收機之寬頻CMOS電路

Design of Broadband CMOS Circuits for UWB and High-Speed Wireline Receivers

廖之帆(Chih-Fan Liao)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2007年)

https://doi.org/10.6342/NTU.2007.10170

摘要

快速成長的無線通訊需求，伴隨著網際網路上與日俱增的資料流通量，帶動了對於寬頻射頻電路與系統的研究興趣。同時，持續演進且縮小尺寸的CMOS製程，使得操作於幾十GHz的高速電路得以用CMOS實現，並與先進通訊系統中龐大的數位電路相整合。體認到寬頻通訊乃大勢所趨，加上CMOS製程的高度整合潛力，驅使本論文從事電路技巧與設計方法的研究，使其可用以實現高速無線與有線應用中的寬頻接收機。
首先，我們提出一個利用寬頻雜訊消除技巧的3.1–10.6-GHz低雜訊放大器。借由我們所提出的電路與設計方法，拿來做匹配的元件所產生的雜訊可在整個超寬頻頻帶內被大幅降低，同時用來消除此雜訊的其他元件，也藉由一套系統化的設計方法來最小化他們本身造成的雜訊。以0.18μm CMOS製作，此晶片最大可提供9.7dB功率增益，具有1.2–11.9-GHz的頻寬，並在整個超寬頻頻帶內保有4.5–5.1dB的雜訊指數。此晶片在1.8V供應電壓下消耗20mW，所佔面積僅0.59mm2。
接下來，我們描述一個10-Gb/s以0.18μm CMOS實現之自動增益控制放大器。這電路使用了一個具有58dB對dB線性控制範圍的可變增益放大器。該控制乃是藉由寄生垂直BJT來實現指數函數的功能。為了操作於10-Gb/s，接於可變增益放大器後的增益級使用了電容性的與並聯-串聯 (shunt-series) 電感性的翹起 (peaking) 技巧。在每邊18m到1Vpp的輸入範圍內，輸出的差動振幅均為430mVpp左右，上下變化約+0.4到–0.8dB。在位元錯誤率 (BER) 小於10–12的條件下，量到的動態範圍為35dB。此電路在不包括輸出緩衝器的情況下自1.8V供應電壓消耗了54mW。
正如人們所熟知的，高速的前端放大器與時脈資料回復電路在寬頻資料接收機中扮演著重要的角色，因為前者須操作在高速下進行信號放大，而後者須淬取出低擾動時脈並以此重新回復資料。接下來的這章呈現關於40-Gb/s轉阻自動增益控制放大器與時脈資料回復電路的設計與實驗結果。轉阻放大器使用了一反向的三次共振網路，並在共閘級的架構下加入了負回授。我們提出了一數學模型以利於反向三次共振網路的設計與分析。我們並且證明了它比並聯-串聯翹起技巧更能延展頻寬，特別是寄生電容主要來自下面一級電路時。此放大器在40-Gb/s操作速度下提供2k歐母的增益，並於輸入為440µ到4mApp範圍內產生520mVpp的差動輸出振幅，同時保持位元錯誤率低於10–9。量測到的全頻帶積分雜訊，等效到輸入端為3.3µArms。時脈資料回復電路為一半速率 (half-rate) 架構，使用了一可確定方向的旋轉波 (rotary-wave) 四相位壓控震盪器，以解決傳統旋轉波震盪器中的雙繞向問題。此做法可確保相位順序，而幾乎不影響相位雜訊。在40-Gb/s 231–1近似亂數位元順序 (PRBS) 的輸入下，回復的時脈抖動為0.7psrms與5.6pspp。重新回復的資料呈現13.3pspp的抖動，位元錯誤率低於10–9。兩電路均以90nm數位CMOS製程製造，皆以1.2V為供應電壓，整個放大器消耗75mW，時脈資料回復電路不包括輸出緩衝器消耗48mW。
最後，我們提出了一個40-Gb/s序列連結 (serial-link) 接收機，包括了一可適性等化器及一個時脈資料回復電路。我們使用了一平行路徑 (parallel-path) 的等化濾波器來補償經過銅纜線的高頻損耗。藉由只改變高通路徑的增益來提供可適性，此架構僅需單一迴路即可適當控制，並省卻了用於分別淬取高低頻信號資訊的RC濾波器。在接於其後的時脈資料回復電路中，我們提出了一個全速率 (full-rate) 的砰砰 (bang-bang) 相位偵測器 (phase detector)，僅需要5個閂 (latch)。最少化閂的數目節省了電源消耗及電感所佔的面積，避免了複雜的高頻訊號繞線也增進了效能。40-Gb/s資料通過4公尺在20-GHz具10dB損耗的纜線，仍可由此接收機回復。在27–1近似亂數位元順序的輸入下，回復的資料輸出振幅為500mVpp，抖動為9.6pspp，位元錯誤率低於10–12。此接收機以90nm CMOS製程製造，消耗了115mW，其中等化器占58mW，時脈資料回復電路占57mW。

關鍵字

寬頻 ； 超寬頻 ； 高速

並列摘要

The rapidly-growing demand for high-speed wireless connections and the tremendous increase of data volume transported over the Internet have stimulated interest in broadband RF circuits and systems. Concurrently, the continuous scaling of CMOS technology has opened the opportunity to integrate high-speed circuits operating at tens of gigahertz together with the large digital portion of modern communication systems. While recognizing the inevitable trend of broadband communication as well as the huge potential of CMOS technology, this dissertation targets on circuit techniques and design methodologies that facilitate the realization of broadband CMOS receivers for high-speed wireless/wireline applications.
First of all, an ultra-wideband 3.1–10.6-GHz low-noise amplifier employing a broadband noise-canceling technique is presented. By using the proposed circuit and design methodology, the noise from the matching device is greatly suppressed over the desired UWB band, while the noise from other devices performing noise cancellation is minimized by the systematic approach. Fabricated in a 0.18-μm CMOS process, the IC prototype achieves a power gain of 9.7 dB over a –3dB bandwidth of 1.2–11.9-GHz and a NF of 4.5–5.1 dB in the entire UWB band. It consumes 20 mW from a 1.8 V supply and occupies an area of only 0.59 mm2.
Next, a 10-Gb/s automatic gain control (AGC) amplifier implemented in 0.18μm CMOS technology is described. The circuit incorporates a linear-in-dB controlled variable gain amplifier (VGA) with 58dB tuning range, which is achieved by utilizing parasitic vertical BJTs to generate the exponential function. To operate at 10-Gb/s, capacitive and shunt-series inductive peaking techniques are applied to the gain stages following the VGA. For input swings from 18m to 1Vpp per side, the differential output swing is 430mVpp within +0.4 to –0.8dB variation. The measured dynamic range is 35dB with BER< 10–12. The circuit consumes 54mW from a 1.8V supply excluding the output buffer.
As everyone knows, high-speed front-end amplifiers and CDR circuits play critical roles in broadband data receivers as the former needs to perform amplification at high data rate and the latter has to retime the data with the extracted low-jitter clock. The following chapter presents the design and experimental results of 40-Gb/s transimpedance-AGC amplifier and CDR circuit. The transimpedance amplifier incorporates reversed tripe-resonance networks (RTRNs) and negative feedback in a common-gate configuration. A mathematical model is derived to facilitate the design and analysis of the RTRN, showing that the bandwidth is extended by a larger factor compared to using the shunt-series peaking technique, especially in cases when the parasitic capacitance is dominated by the next stage. Operating at 40-Gb/s, the amplifier provides an overall gain of 2kΩ and a differential output swing of 520mVpp for input spanning from 440µApp to 4mApp, with BER< 10–9. The measured integrated input- referred noise is 3.3µArms. The half-rate CDR circuit employs a direction-determined rotary- wave quadrature VCO to solve the bidirectional-rotation problem in conventional rotary-wave oscillators. This guarantees the phase sequence while negligibly affects the phase noise. With 40-Gb/s 231–1 PRBS input, the recovered clock jitter is 0.7psrms and 5.6pspp. The retimed data exhibits 13.3pspp jitter with BER< 10–9. Fabricated in 90nm digital CMOS technology, the overall amplifier consumes 75mW and the CDR circuit consumes 48mW excluding the output buffers, all from a 1.2V supply.
Finally, a 40-Gb/s serial-link receiver including an adaptive equalizer and a CDR circuit is presented. A parallel-path equalizing filter is used to compensate the high-frequency loss in copper cables. The adaptation is performed by only varying the gain in the high-pass path, which allows a single loop for proper control and completely removes the RC filters used for separately extracting the high- and low-frequency content of the signal. A full-rate bang-bang phase detector with only 5 latches is proposed in the following CDR circuit. Minimizing the number of latches saves the power consumption and the area occupied by inductors while improving the performance by avoiding complicated routing of high-frequency signals. The receiver is able to recover 40-Gb/s data passing through a 4m cable with 10dB loss at 20-GHz. For an input PRBS of 27–1, the recovered clock jitter is 0.3psrms and 4.3pspp. The retimed data exhibits 500mVpp output swing and 9.6pspp jitter with BER< 10–12. Fabricated in 90nm CMOS technology, the receiver consumes 115mW, of which 58mW is dissipated in the equalizer and 57mW in the CDR.

並列關鍵字

broadband ； CMOS ； UWB ； high-speed

參考文獻

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