利用代表性隨機漫步演算法應用於全速測試之暫態電壓降分析

Transient IR-drop Analysis for At-speed Testing Using Representative Random Walk

蔡旻宏(Ming-Hong Tsai)

指導教授 ： 李建模

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2012年)

https://doi.org/10.6342/NTU.2012.01888

摘要

本論文提出了一個代表性隨機漫步的演算法應用在快速暫態電壓降分析。代表性隨機漫步演算法只有選擇少量的節點來建構原本電路的模型，使得記憶體使用量和執行時間可以大大地減少。從大型測試電路的實驗數據當中顯示，我們所提出的方法和商用模擬器相比，速度比它快了高達330倍並且平均誤差不超過10%。除此之外，模擬所有2萬6千個延遲錯誤測試向量和40萬邏輯閘的電路，可以在一個星期內完成。此提出的方法在全速測試中模擬每個測試向量的捕獲週期是非常有用的，它可以找出那些具有過大電壓降的測試向量。

關鍵字

電壓降 ； 暫態分析 ； 全速測試

並列摘要

This thesis presents a representative random walk technique for fast transient IR-drop analysis. Representative random walk selects only a small number of nodes to model original network for simulation so that the memory and run time are significantly reduced. Experimental results on large benchmark circuits show that our proposed technique can be up to 330 times faster than a commercial simulator while the average error is less than 10%. Furthermore, the exhaustive simulation of all 26K delay fault test patterns on a 400K-gate design can be finished within a week. The proposed technique is very useful to simulate capture cycles to identify test patterns that cause excessive IR drop during at-speed testing.

並列關鍵字

IR drop ； transient analysis ； at-speed testing

參考文獻

[Ahmed 07] N. Ahmed and M. Tehranipoor, “Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design,” Proc. of Design Automation Conference, 2007, pp. 533-538.

[Arabi 07] K. Arabi, R. Saleh, and X. Meng, ‘‘Power Supply Noise in SoCs: Metrics, Management, and Measurement,’’ IEEE Design & Test, vol. 24, no. 3, 2007, pp. 236-244.

[Bunch 74] J.R. Bunch and J.E. Hopcroft, “Triangular factorization and inversion by fast matrix multiplication,” Mathematics of Computation, 1974, pp. 231–236.

[Butler 04] K. M. Butler, J. Saxena, T. Fryars, G. Hetherington, A. Jain, and J. Lewis, “Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques,” Proc. Int. Test Conf., 2004, pp.355–364.

[Chen 97] Chen H. H., Ling D. D., “Power supply noise analysis methodology for deep-submicron vlsi chip design,” In Proceedings of the 34th Annual Design Automation Conference. ACM, New York, 638–643.