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  • 學位論文

引入數位微分器之連續時間三角積分調變器與無帶隙參考電壓之電阻式溫度感測器設計

Design of Digital-Differentiator-Embedded Continuous-Time Delta-Sigma Modulator and Bandgap-Reference-Free Resistor-Based Temperature Sensor

指導教授 : 林宗賢

摘要


本篇論文分為兩個部分:第一部分是提出一個引入數位微分器的連續時間型三角積分調變器架構,其目的是為了解決延遲迴路效應,以及減少數位類比轉換器數量,進而解決數位類比轉換器的非線性問題;第二部分是提出一個無帶隙參考電壓的電阻式溫度感測器,其目的是為了解決前端類比電路設計的複雜度,進而實現一操作在高速、低功率之溫度感測器。 連續時間型三角積分調變器目前普遍提出的架構以低通三角積分調變器為主,已被廣泛的被研究和使用,而提高訊號雜訊比的方法,第一,可提高超取樣速率,減少頻寬內量化雜訊的能量,然而,超取樣速率的提升會造成操作速度的增加,如此一來便會增加積分調變器的能量消耗;且在連續時間型三角積分調變器中,取樣頻率過高也會造成延遲迴路,影響整個系統的穩定性;第二,增加電路階數,但相對的系統穩定度還有功率消耗都會是個問題。另外一個可以提升訊號雜訊比的辦法即是增加量化器的位元數,但是對於多位元的三角積分調變器中,數位類比轉換器間的非線性問題會是一項挑戰。 總結上述,我們提出一個多位元的三角積分調變器來提高訊號雜訊比,並引入一個數位微分器的機制使得回授的數位類比轉換器數量大幅減少,解決DAC非線性問題,同時也可針對延遲迴路效應做補償,使整個系統更趨穩定。使用台積電0.18微米互補式金氧半製程,實現一個二階四位元連續時間型三角積分調變器,經過電路層次的模擬,使用64 MHz的取樣頻率,在1 MHz的頻寬下,可得到74 dB的訊號雜訊比,在1.8伏特的供應電壓下,消耗6 mW的功率。 由於先進製程的趨勢,使電路密集整合在中央處理器內,容易產生過熱的問題,因此需要一個快速偵測的溫度感測器,及時反映當時的溫度,並且做回授控制。本論文第二部分的核心概念是使用電阻來當作溫度感測的元件,並提出一個無帶隙參考電壓的類比數位轉換器之架構,有別於傳統上所使用雙載子接面電晶體為主體的溫度感測器,我們使用一個不規則阻值間距之電阻串來產生參考電壓與輸入訊號做比較,此架構所帶來的好處是可以減少前端類比電路的複雜度,以及降低功率消耗。使用台積電0.18微米互補式金氧半製程,實現一可達到0.125°C的解析度,溫度感測範圍是-40°C~120°C,核心面積為0.23 mm2,在1.8伏特的供應電源下,消耗36 uW的功率。

並列摘要


This thesis consists of two parts: PART1 presents a continuous-time delta-sigma modulator with a digital differentiator for the purpose of excess loop compensation and reducing the number of digital-to-analog converter (DAC) element to solve the DAC nonlinearity issue. PART2 presents a bandgap-reference-free resistor-based temperature sensor for the purpose of relaxing the complexity of the design of front-end circuits, and furthermore, operating in high-speed and low-power environments. Low-pass structure has been widely used in continuous-time delta-sigma modulator. The approaches to improve signal-to-noise ratio (SNR), first, is increasing over-sampling ratio (OSR) to reduce in-band noise power, however, high OSR results in high operation speed and more power consumption. Also, the excess loop delay issue may even worse. Second, increasing the order of loop filter can also improve SNR, but stability and power consumption are still the major problems. Another way to improve SNR is using a multi-bit quantizer, but the nonlinearity of multi-bit DAC is a challenge. Above all, we proposed a multi-bit delta-sigma modulator with a digital differentiator to compensate excess loop delay effect and largely reduce the number of DAC elements to solve the nonlinearity issue. The 2nd-oder 4-bit continuous-time (CT) delta-sigma modulator (DSM) is implemented in TSMC 0.18-um 1P6M process, this work can achieve resolution of 0.125°C, the temperature range is -40°C~120°C, core area is 0.23 mm2, and power consumption is 36 uW under 1.8-V power supply.

參考文獻


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