平行測試晶片網路之方法

A Concurrent NoC Testing Methodology

許燦森(Tsan-Sen Hsu)

指導教授 ： 黃俊郎

國立臺灣大學/電機資訊學院/電機工程學研究所/碩士(2012年)

https://doi.org/10.6342/NTU.2012.10560

摘要

隨著積體電路設計複雜度不斷地提高，傳統系統晶片(SoC)導向的設計方法漸漸式微，取而代之的是更具設計彈性、擴充性、可靠度與容錯能力的網路晶片(NoC)，有別於系統晶片運用匯流排架構溝通方式，網路晶片模擬網際網路溝通原理，將許多簡易的小型路由器有規律地安置在網路晶片中，而這些路由器負責模組間封包的傳遞。
然而，網路晶片在積體電路測試上是一大挑戰，第一、由於路由器彼此相互連線的特性，使得測試接點過少，造成注入測試圖樣的不易，提高測試的困難度，第二、若利用傳統掃描測鏈(scan chain)方式測試，隨著正反器數目的增加，往往造成過長的測試時間，第三、路由器間的接線亦需額外測試，因為接線間也有發生斷路或短路的可能性。
在本論文中，我們將周邊掃描單元(boundary scan cell)加入網路晶片中提高可測試性，並且可利用功能測試(functional test)完整地測得先進先出緩衝器錯誤；至於其餘邏輯元件部分，由實驗結果得知，定值錯誤(stuck-at fault)與轉換錯誤(transition fault)的錯誤覆蓋率分別可達99.62%與95.78%。

關鍵字

VLSI testing ； NoC ； fault tolerance

並列摘要

As the complexity of VLSI design scales, we are unlikely to adopt traditional SoC design method. Instead, network-on-chip (NoC) – a new SoC paradigm was formally proposed in 2002 which possesses more flexibility, scalability, reliability and the ability of fault tolerance. NoC simulates the communication mechanism of computer network, that is, it replaces the bus architecture with many simple routers. These routers are responsible for communications between modules.
However, NoC testing is a big challenge. First, because all routers in NoC are connected with nearby router, it is not easy to inject test pattern due to lack of test access point. Second, if we adopt traditional scan-based method, we will suffer from long testing time as flip-flop number increases. Third, we also need to consider interconnect fault between two nearby routers because open/short fault is likely to exist among these nets.
In this thesis, we insert specific boundary scan cell into NoC for improving testability. Besides, we can test FIFO faults completely by functional test. And from experimental result, the fault coverage of remaining logic elements is 99.62% in stuck-at fault model and 95.78% in transition fault model.

並列關鍵字

積體電路測試 ； 晶片網路 ； 容錯

參考文獻

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