以壓控振盪器為基礎且具線性校正技術之三角積分調變器

本論文提出如何校正以壓控振盪器為基礎之三角積分器所面臨的非線性影響，特別是校正諧波所導致整體效能的降低。在本論文中，以壓控震盪器為基礎之三角積分器皆為開路操作，雖然開路操作可以避免掉穩定度還有迴授補償延遲的問題，但在整個系統所產生的非理想效應皆會直接的反應在輸出而導致整體效能降低，在所有的非理想效應之中，以壓控震盪器所產生的諧波失真最為嚴重，所以本論文的重心也將就諧波失真的問題進行探討，並提出解決方法。本論文使用兩種不同的方法來矯正非線性效應的影響-其一前景矯正，使用一測試信號來偵測輸入到輸出的變化，從而導出非線性的係數並加以還原。其二為背景矯正，使用一參考三角積分器來達到矯正非線性的目的。兩者皆為使用台積電90 nm互補式金氧半製程所實現，使用500 MHz的取樣頻率在10 MHz的頻寬，1.2伏特的供應電源時，分別消耗20毫瓦跟12毫瓦的功率

關鍵字

壓控振盪器；三角積分器

並列摘要

This thesis presents two calibration techniques to address the linearity issue in VCO-based delta-sigma modulator. Unlike conventional delta-sigma modulator, the VCO-based delta-sigma modulator operates in a open-loop manner which avoids the stability and excess loop delay (ELD) issues. However, the non-linear effect is not suppressed by the loop as it affects output directly. Among all the non-linear effects, the harmonic distortion from VCO is the worst and needs to be addressed. The first technique utilizes the foreground calibration to recover the distorted output signal. The nonlinearity is detected by sending a fixed input pattern. In the second technique, the background calibration is presented. The nonlinearity of VCO is corrected based on the additional reference ADC. These two techniques are implemented in a TSMC 90-nm CMOS process. The system bandwidth is designed 10 MHz with 500 MHz sampling frequency. The implemented modulator dissipate 20 mW and 12 mW respectively from a 1.2-V supply.

並列關鍵字

VCO ； Delta-Sigma Modulator

參考文獻

[2] P. Silva, L. Breems, K. Makinwa, R. Roovers, and J. Huijsing , “An IF-to-Baseband ΣΔ Modulator for AM/FM/ IBOC Radio Receivers With a 118 dB Dynamic Range”, IEEE J. Solid-State Circuits, vol. 42, 1076-1089, May 2007.

[4] M. Park and M. H. Perrott, ” A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-time ΔΣ ADC with VCO-Based Integrator and Quantizer Implemented in 0.13 μm CMOS,” IEEE J. Solid-State Circuit, vol. 44, pp. 3344-3358, no. 12, Dec. 2009.

[5] J. Hamilton, S. Yan, and T. R. Viswanathan, “A Discrete-Time Input ΔΣ ADC Architecture Using a Dual-VCO-Based Integrator,” IEEE J. Solid-State Circuits, vol. 57, no. 11, pp. 848–852, Nov. 2010.

[6] M. Z. Straayer, and M. H. Perrott, “A 12-Bit, 10-MHz Bandwidth, Continuous-Time ΔΣ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 805–814, Apr. 2008.

[7] J. Kim, T.-K. Jang,Y.-G. Yoon, and S.-H. Cho, “Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter,” IEEE Transactions on Circuits and Systems—I: regular papers, vol. 57, no. 1, Jan. 2010.

國際替代計量

以壓控振盪器為基礎且具線性校正技術之三角積分調變器

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