本論文採用了不完全趨穩的技巧,提出了背景調整取樣時間校正來實現一個 六位元、每秒十億次取樣的導管式類比數位轉換器。不完全趨穩的技巧伴隨著背 景調整取樣時間校正能夠降低類比數位轉換器中運算放大器對於增益和頻寬的需 求從而降低運算放大器的功率消耗。 本晶片使用台積電 65nm CMOS 一般製程製作。根據量測結果,在1 GS/s 的 轉換率下的DNL 和INL 分別為+0.72/-0.68 LSB 和+0.76/-0.68 LSB。在輸入頻率為499.0 MHz 且在1 GS/s 的轉換率下時,SNDR 和SFDR 分別為33.39 dB 和41.03dB。然而在輸入頻率為9.7 MHz 且在900 MS/s 的轉換率下時,SNDR 和SFDR 分別為35.17 dB 和49.50 dB。在1 V 的電壓和1 GS/s 的轉換率下的功率消耗為62 mW。全部的晶片面積大小為0.89 mm2,然而主動電路所占的面積只有0.30 mm2。
This thesis adopts incomplete-settling technique and proposes background sampling-point calibration to realize 6-bit, 1GS/s pipelined ADC. Incomplete-settling technique with proposed background sampling-point calibration allows low-gain and low-bandwidth opamp to be used and lowers the power consumption of opamp. This prototype ADC is fabricated in TSMC 65nm CMOS general-process. According to measurement results, this prototype ADC exhibits DNL of +0.72/-0.68 LSB and INL of +0.76/-0.68 LSB at sampling rate of 1 GS/s. SNDR and SFDR are 33.39 dB and 41.03 dB at 1 GS/s with 499.0 MHz input frequency. But at 900 MS/s with 9.7 MHz input frequency, SNDR and SFDR are 35.17 dB and 49.50 dB. The power consumption is 62 mW at 1 V supply voltage and 1 GS/s sampling rate. Active area is 0.30 mm2, and whole chip with pads occupies 0.89 mm2.