基於卷積神經網絡的硬體描述語言設計之探勘

Hardware Description Language Design Exploration by Convolutional Neural Network

盧毅鴻(Yi-Hong Lu)

指導教授 ： 黃鐘揚

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2017年)

https://doi.org/10.6342/NTU201703659

摘要

基於卷積神經網絡的硬體描述語言設計之探勘是一種幫助工程師快速理解硬體描述語言設計意圖的新技術。在我們的研究中，主要探討的硬體描述語言是Verilog，我們成功的將深度學習的技術應用在傳統的電子自動化設計的問題上。我們使用卷積神經網絡來擷取硬體描述語言設計的意圖，並提出了一種新的資料結構稱為設計相依圖。它提供了電路意圖的預測資訊，以及一個方便理解電路的閱讀程式碼的順序的資訊給工程師，讓他們可以有方法有效率地去理解電路。在電子自動化設計領域，這是一個非常新穎的想法，因為我們把深度學習訓練的單位下降到一個always@ blocks，並且得到了良好的結果。而為了幫助工程師更有效率的理解電路，我們更發了一個線上的硬體描述語言設計探勘的平台，稱之為X-HDL。X-HDL提供了一個使用者友善的介面，以及具互動性的功能，讓硬體描述語言設計探勘的目的發揮得更極致。

關鍵字

卷積神經網絡 ； 設計意圖探勘 ； 設計相依圖

並列摘要

Hardware description language design exploration by convolutional neural network is a novel technique to help designers to understand HDL design intent quickly. The major hardware description languages we use in this work is Verilog. We successfully applied the technology of deep learning to the traditional EDA problem. We use CNN techniques to extract the intent of HDL design in RTL level, and propose a new data structure called DDG to provide the designer with a structured information and a good order of code for reading to understand the design. This is a very original idea in the field of EDA, because we narrowed down the units of design intent classification to always@ blocks in RTL level, and got a good experimental result. In order to provide a more effective way to help designers understand design intentions, we have developed an online HDL design exploration tool called X-HDL. X-HDL provides a user-friendly and interactive feature that makes the HDL design exploration more useful.

並列關鍵字

HDL exploratio ； Design Intent ； Classification ； Dependency Graph

參考文獻

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