快捷資料列搬移機制在非對稱式次陣列動態隨機存取記憶體中的應用

在過去十年間,DRAM(動態隨機存取記憶體)科技的發展持續不斷的在追求產品的容量與傳輸頻寬。相較之下,DRAM 的存取時間在這十年中並沒有大幅度的進展。在 DRAM 產品中採用較短的 bitline 可以有效的縮短DRAM 存取時間,但是另一方面這個方法會影響 DRAM 中陣列的密度。在主要的產品市場中,製造商並不樂意以密集度換取存取時間。因此過去的研究中 [1, 2],曾經提出以複合式 bitline 的設計來解決這個問題。在同一顆DRAM 晶片中,以長短不同的 bitline 分別構成的速度與密度不同的兩個區域,藉此平衡較短 bitline 對於陣列密度所帶來的衝擊。但是,我們觀察到過去研究中幾個主要的缺點,例如在 TL-DRAM 中 [1],所採用的設計對於陣列具有侵入性,或者在非對稱式次陣列 DRAM 中 [2],不同區域間沒有搬移資料列的機制。在這篇論文中,我們提出一個創新且快捷的方法,讓資料列可以在兩個次陣列間搬移,並將這個方法應用在非對稱式次陣列 DRAM 中 [2]。再者我們探索了許多管理的策略,並提出一套簡單的管理機制。我們的實驗結果顯示加入了資料列搬移與管理機制後,我們可以分別在單執行序與多執行序的環境中,達到平均 7.25%與 11.77%的效能提昇。這些數字已經超過理想中全部以較短 bitline 所組成的 DRAM 效能的 80%。

關鍵字

動態隨機存取記憶體；非對稱式次陣列；資料列搬移

並列摘要

The evolution of DRAM technology has been driven by capacity and bandwidth during the last decade. In contrast, DRAM access latency stays relatively constant and is trending to increase during the same period. Having smaller bitline length in a DRAM device will reduce the device access latency. However by doing so it will impact the array efficiency. In the mainstream market, manufacturers are not willing to trade capacity for latency. Prior works [1, 2] had proposed hybrid-bitline DRAM design to overcome this problem. They hybrid long and short bitline designs on the same chip to form fast and slow levels, and the capacity lost is amortized. However, the main drawbacks of those methods are either intrusive to the circuit design [1], or there’s no direct way to migrate data between the fast and slow level [2]. In this paper, we proposed a novel and low cost way to allow data to migrate between subarrays. Applying this design to asymmetric sub-array DRAM, we proposed a simple management mechanism and explored many management related policies. We showed that with this new design and simple management technique we could achieve 7.25% and 11.77% performance improvement in single- and multi-programming workloads, respectively over a system with traditional homogeneous DRAM. This gain is above 80% of the potential performance gain of a system based on a hypothetical DRAM which is made out of short bitlines entirely.

並列關鍵字

DRAM ； Asymmetric Subarray ； Data Migration

參考文獻

and Onur Mutlu. Tiered-latency dram: A low latency and low cost dram architec-

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of the 40th Annual International Symposium on Computer Architecture, ISCA ’13,

Changyoung Lee, Jin-Il Lee, Hyoung-Joo Kim, Min Soo Jang, Gong-Heum Han,

Kihan Kim, Daesik Moon, Seungjun Bae, Joon-Young Park, Kyung-Soo Ha, Jae-

國際替代計量

快捷資料列搬移機制在非對稱式次陣列動態隨機存取記憶體中的應用

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