高效節能時脈系統設計

Design of a High-Performance Energy-Efficient Clock Generation System

林君豫(Chun-Yu Lin)

指導教授 ： 林宗賢

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2022年)

https://doi.org/10.6342/NTU202200083

摘要

在系統中需要多組不同的時脈來提供給不同的模組運作。本篇論文提出一高效節能之時脈系統架構，著重在只使用單一晶體來實現兆赫茲與低功耗千赫茲輸出並降低溫度效應下所造成的頻率偏移。此架構共包含為四個作品如下所述。
本論文的第一個晶片為溫度補償晶體震盪器，實現於180奈米製程。我們使用多組受電壓控制電容來逼近一個多項次補償函數。用此方式來取代傳統複雜的補償，可以有效地節省面積與功耗。在攝氏-30度到90度的溫度範圍下可將溫度偏移由 ±12 ppm改善至 ±3.75 ppm，此晶片面積為0.282平方毫米。
本論文第二個晶片32.768千赫茲時脈產生器，實現於180奈米製程。我們提出一頻率校正系統，重複使用時脈系統內的唯一一顆兆赫茲晶體來產生千赫茲輸出並且維持整體功耗小於1微安培，在極端的溫度範圍以一兩位元溫度感測器做偏移補償。在攝氏-50度到105度的範圍內達到±20 ppm的頻率偏差，此晶片面積為0.364平方毫米。
本論文第三顆晶片為一整數倍率時脈產生器用於提供開迴路小數除頻器的輸入訊號，實現於90奈米製程。我們使用次取樣來穩定迴路使其能夠使用注入式鎖定之技術來實現高效能的時脈輸出。在晶片面積0.26平方毫米以及0.5毫瓦功耗下，產生一2.4千兆赫茲370飛秒的時脈抖動之輸出頻率。
本論文第四顆晶片為一開迴路小數除頻器，實現於90奈米製程。在此作品中我們大幅度的降低最佔功耗與面積的數位時間轉換器模組，因此能夠於0.008平方毫米的面積下產生0.625-200兆赫茲的時脈輸出並且達到300飛秒的時脈抖動以及1.5毫瓦的功耗。

關鍵字

溫補震盪器 ； 千赫茲震盪器 ； 高效鎖相迴路 ； 開迴路小數除頻器

並列摘要

In this thesis, we proposed a high-performance energy-efficient clock generator system, which supports MHz and low-power kHz output with good temperature accuracy. This system consists of four works as follows:
The first chip is a temperature-compensated crystal oscillator, realized in the 180-nm CMOS process. The proposed piecewise polynomial varactor to replace the complicated digital mapping compensation scheme for reducing power consumption and chip area. From -30 °C to 90 °C, the frequency inaccuracy improves from ±12 ppm to ±3.75 ppm, and it occupies 0.282 mm2 chip area.
The second chip is a 32.768-kHz clock generator, realized in the 180-nm CMOS process. The proposed a calibration scheme reuses the system clock to generate kHz output under 1-uA current consumption. At the extreme temperature, a 2-b temperature sensor is used for compensation. It achieves ±20 ppm from -50 °C to 105 °C, and it occupies 0.364 mm2 chip area.
The third chip is an integer-N PLL, realized in the 90-nm CMOS process. The proposed sub-sampling sub-harmonically injection-locked technique to achieve high-performance clock output. The output frequency is 2.4 GHz with 370 fs jitter, and it consumes 0.26 mm2 chip area and 0.5 mW power consumption.
The fourth chip is a fractional output divider, realized in the 90-nm CMOS process. The digital-to-time converter (DTC) dominates power and area in the system. In this work, we proposed the replica-DTC-free background calibration scheme to improve performance. From measurement results, it generates 0.625-200 MHz output clock with 300 fs jitter under 1.5 mW and 0.008 mm2.

並列關鍵字

TCXO ； kHz clock generator ； high-performance PLL ； fractional output divider

參考文獻

Simplify Timing Architectures with Flexible Clocks, accessed on May 2021 [Online]. Available: https://www.silabs.com/timing/clock-generators/multisynth

The Value of Fractional Output Divider PLLs for Infotainment and Dashboard Applications, accessed on May 2021 [Online]. Available: https://www.renesas.com/us/en/blogs/value-fractional-output-divider-plls-infotainment-and-dashboard-applications

Any-Frequency 1–200 MHz Quad Frequency 8-Output Clock Generator Datasheet, accessed on May 2021 [Online]. Available: https://www.silabs.com/documents/public/data-sheets/Si5355.pdf

Programmable Clock Generator Datasheet, accessed on May 2021 [Online]. Available: https://www.renesas.com/us/en/document/dst/5p49v5923-datasheet

VersaClock® 3S Programmable Clock Generator Datasheet, accessed on May 2021 [Online]. Available: https://www.renesas.com/us/en/document/dst/5l35021-datasheet?language=en