消費性電子進階配接器系統之匯流排功能性模型

Bus Function Models for the Consumer Electronics - Advanced Technology Attachment System

吳則霖(TES-LIN WU)

指導教授 ： 郭斯彥

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2006年)

https://doi.org/10.6342/NTU.2006.00923

摘要

隨著SOC複雜度的快速成長，驗證所需要的模擬時間也就越來越長，使得效率大打折扣。也因此，傳統的硬體驗證方式就越來越趕不上腳步。要如何節省驗證的時間是目前非常重要的一個課題。
為了解決上述的問題，本論文提出了一套Consumer Electronics Advanced Technology Attachment (CE-ATA)的匯流排功能性模組(Bus Functional Model)。並且利用Verilog行為語法以及驗證語言擴增(Verification Language Extension)工具的輔助來實作。 此外，本論文還利用了transaction based, assertion based, coverage based來建構出一個驗證環境，以求能夠對CE-ATA的晶片設計者提供更大的幫助。

關鍵字

配接器 ； 消費性電子

並列摘要

As the rapid growth of the complication of SOC, the simulation time spent on verification is getting longer and longer, which results in low efficiency. That is why the traditional method of verification started to be left behind. How to save the time on verification is a very important issue nowadays.
To solve the above problem, this thesis represents a set of Bus Functional Model (BFM) of Consumer Electronics ATA (CE-ATA), and uses tools such as Verilog behavior language and verification language extension. Besides, this thesis also uses several methodologies, transaction based, assertion based, coverage based, to build a verification environment, in order to offer greater help for the chip designer of CE-ATA.

並列關鍵字

ATA ； CE

參考文獻

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