IEEE 802.11a頻率合成器之設計與實作

Design and Implementation of a Frequency Synthesizer for IEEE 802.11a

李中傑(Chung-Chieh Lee)

指導教授 ： 陳少傑

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2006年)

https://doi.org/10.6342/NTU.2006.10153

摘要

這幾年以來，無線通訊的發展日新月異，無線通訊無疑是未來的科技趨勢，為了因應市場需要，各種通訊協定紛紛制定，像是IEEE 802.11b，UWB，WiMAX，IEEE 802.11n等等。其中，IEEE 802.11a無線通訊協定選用國家通訊公用(UNII)的頻帶(5.15GHz ~ 5.35GHz，5.725GHz ~ 5.825GHz)來進行傳輸，並採用正交分頻多工調變(OFDM)，此頻帶可以提供高速的資料傳輸(54Mbp)，使得此協定和在2.4GHz頻帶的通訊協定(802.11b/g)相比下，能吸引更多無線通訊鏈結以此協定作產品實現。
在無線接收機的電路中，常利用鎖相迴路(phase-locked loop,PLL)的機制把接收到的信號和時脈作同步，才能進一步將訊號利用分析。而將鎖相迴路此種機制應用在無線收發機中,稱為頻率合成器，或是本地震盪器。頻率合成器在射頻電路中是一不可或缺的要件，設計一個兼具快速鎖定時間，低相位雜訊和高頻率解析度的頻率合成器也是許多論文在探討的問題。
802.11a的訊號動態範圍很大以及傳輸頻寬很寬，若將系統中的頻率合成器整合進入晶片之內，在相位雜訊(phase noise)和參考頻雜訊(reference noise)都將會面臨嚴苛的挑戰。為了涵蓋IEEE 802.11a如此寬的工作範圍，以及因元件製程與溫度上的變異，鎖相迴路中的壓控振盪器(voltage-controlled oscillator, VCO)將會是此系統關鍵。通常希望壓控振盪器具有很低的增益(Kvco)，雖然許多文獻上有討論如何使壓控振盪器不具高增益，然而它們仍無法在如此高的操作頻率上，同時達到高頻寬與低雜訊敏感度。壓控振盪器本身幾乎決定了頻率合成器的相位雜訊，也決定了頻率合成器的輸出頻率，因此設計一良好的壓控振盪器是十分重要的一環。
本論文設計了應用於IEEE 802.11a通訊協定的頻率合成器，利用MASH 1-1-1的三角積分調變器改善頻率合成器輸出相位雜訊的影響，另外由積體電路實現一除小數之頻率合成器，利用三角積分調變作為除頻器之調變，藉由打亂除頻器模數，將傳統除小數頻率合成器所產生的小數突波(fractional spur)推至高頻，再經由鎖相迴路濾除。在此使用0.18μm CMOS製程，除了成本考量外，另一方面是因為CMOS在未來的系統中具有高度的整合效果。

關鍵字

頻率合成器 ； 802.11a

並列摘要

Nowadays, local oscillator is an essential component of the RF front-end. For market need, many kinds of wireless protocols have been setup, like IEEE 802.11b, UWB, WiMAX, IEEE 802.11n, etc. IEEE 802.11a is one of them using UNII band (5.15GHz ~ 5.35GHz，5.725GHz ~ 5.825GHz) and by OFDM to transmit data. This band allows high speed data communications (54Mbs), so becomes more attractive and fascinates more realization of wireless link and mobile communication, compared to the 2.4GHz (802.11b/g) counterpart.
In wireless transceiver design, we often use a phase-locked loop (PLL) circuit to synchronize the receiving signal and the receiving clock and then to analyze the signal. The PLL circuit used in wireless transceiver is called frequency synthesizer, or local oscillator. Frequency synthesizer is a very important component of RF circuit. And the design of a frequency synthesizer with agile settling speed, low phase noise and high frequency resolution has become a challenge.
It has been well acknowledged that integration of an RF frequency synthesizer into a transceiver poses great challenge because the large dynamic range of the input signal and wide channel bandwidths have set stringent requirements for the synthesizer phase noise and spurious sideband levels. To cover such a wide tuning range and overcome the temperature and process variation, the voltage-controlled oscillator in a frequency synthesizer is the key point. Usually we need a low gain of VCO (KVCO). While techniques to avoid large KVCO have been developed, the characteristics of wide range and low sensitivity still cannot be realize concurrently in that high frequency of 5GHz. Voltage-controlled oscillator almost dominates the phase noise of a frequency synthesizer and determines the output frequency of frequency synthesizer. So it is the key point to design a good VCO.

This Thesis discusses the influence of the MASH Sigma-Delta Modulator (SDM) to the synthesizer output phase noise. The integrated fractional-N frequency synthesizer is implemented with a MASH 1-1-1 SDM. On one hand, better fractional and reference spurious suppression are achieved by randomizing the modulus of frequency dividers; on the other hand, the spurious noise can be pushed to a higher frequency and will be further filtered out by the PLL.

並列關鍵字

frequency synthesizer ； 802.11a

參考文獻

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