基於平台的FPGA軟硬體共同設計︰以JPEG 壓縮為例

A platform-based HW/SW co-design for FPGA: Using JPEG compression as an example

蔡青峰(Chin Feng Tsai)

指導教授 ： 王勝德

國立臺灣大學/電機資訊學院/電機工程學研究所/碩士(2006年)

https://doi.org/10.6342/NTU.2006.00946

摘要

對於混合軟硬體系統，本篇論文利用基於平台的設計方法去設計硬體加速器，在分割軟硬體的過程我們把焦點放在減少軟硬體的溝通花費，我們設計三種架構的硬體加速器並討論如何去測量溝通花費，使用這測量的結果去切割軟硬體。最後我們去分析得到的效能改進的結果。

關鍵字

混合軟硬體系統 ； 基於平台硬體加速器設計方法 ； 硬體加速器 ； 溝通花費

並列摘要

Aiming to a mixed software/hardware system, in this thesis, we make use of the platform-based methodology to design hardware accelerators on FPGAs. We focused on reducing the hardware/software communication overheads in partitioning the codes. We design three kinds of hardware accelerators on FPGAs and discuss how to measure communication costs. The result of the measurement is then used to divide the codes in a hardware/software that enhances the performances of software. Finally we analyze the performances of our designs.

並列關鍵字

mixed software/hardware system ； platform-based methodology ； hardware accelerators ； commutation cost

參考文獻

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