以波管線為基礎的抖動產生技術應用於高速收發器之內建自我測試

A Wave Pipeline-Based Jitter Generation Technique for High-Speed Transceiver Design-for-Test Applications

張興維(Shing-Wei Chang)

指導教授 ： 黃俊郎

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2006年)

https://doi.org/10.6342/NTU.2006.00968

摘要

在現今的高速通訊元件中，抖動已然成為資料可達到傳送品質的重要因素之一，隨著資料傳送頻寬的需求漸增，抖動的規格對高速傳送系統及匯流排來說是相當重要的。一般而言，元件抖動的規格是由自動測試設備(ATE)所測得，但是資料頻率快速的提升使得自動測試設備難以趕上期效能的要求。再者，近來大多數研究投注在抖動量測的部分。在本論文中，我們提出了一個低成本且可實現在晶片上的週期性抖動注入技術，為了達到系統層之內建式自我測試應用，並利用模擬去驗證我們的方法。

關鍵字

抖動 ； 抖動產生技術

並列摘要

For modern high speed communication devices, jitter has been an important factor of the achievable data transmission quality. With the growing demand on data bandwidth, meeting the jitter specification is crucial for high speed I/O and bus standards. Typically, jitter specifications are tested by external Automatic Test Equipment (ATE), but the growing data rate makes it difficult, if possible at all, for the ATE to catch up with the performance requirement. Most of the recent works concentrate on jitter measurement. In this thesis, a low-cost on-chip sinusoidal jitter injection technique for system level Built-In Self-Test (BIST) applications is proposed. Simulation results are demonstrated to validate the proposed technique.

並列關鍵字

jitter ； design-for-test

參考文獻

[1] Y. Cai, B. Laquai, K. Luehman, “Jitter Testing for Gigabit Serial Communication Transceivers,” IEEE Design & Test of Computers, Volume 9, Issue 1, 2002, pp.64-74

[3] T. Yamaguchi, M. Soma, M. Ishida, H. Musha, L. Malarsie, “A New Method for Testing Jitter Tolerance of SerDes Devices Using Sinusoidal Jitter,” ITC Proceedings, 2002, pp.717-725

[4] J. Wilstrup, “A Method of Serial Data Jitter Analysis Using One-shot Time Interval Measurement,” ITC Proceedings, 1998, pp.819-823

[5] S. Tabatabaei, M. Lee, F. Ben-Zeev, “Jitter Generation and Measurement for Test of Multi-Gbps Serial IO,” ITC Proceedings, 2004, pp.1313-1321

[6] B. Laquai, Y. Cai, “Testing Gigabit Multilane SerDes Interfaces with Passive Jitter Injection Filters,” ITC Proceedings, 2001, pp.297-305