高效能延遲鎖定迴路的設計與應用

延時鎖定迴路(DLL)廣泛地被應用於許多方面，比如多相位時脈(clock)之產生或時脈產生器。此篇論文分別介紹了二種延時鎖定迴路之應用，一為全整合倍化式延時鎖定迴路(multiplying DLL)以及分散式延時鎖定迴路(distributed DLL)。此倍化式延時鎖定迴路使用了廣義阻抗變換器(general impedance converter)以大幅地減少所佔用之晶片面積。而為了解決因廣義阻抗變換器之損耗所造成之問題，提出了可適性電流調整(adaptive current tuning)此技巧。多相位時脈之精準度通常被不同元件之間的不匹配(mismatch)所影響，因此提出了分散式延時鎖定迴路以產生低抖動(jitter)以及高相位準度之時脈，此分散式延時鎖定迴路之特性為不需要額外之相位校準電路。米勒效用廣泛地被使用於增加晶片上之電容，但是放大倍率通常因元件之間的誤差而有所限制。採用了廣義阻抗變換器大幅地增加了晶片上電容達二千倍，有效地縮小晶片面積。此論文詳細地分析隨之而來的非理想性。為了解決這些問題，提出了可適性電流調整此技巧。此時脈產生器之基本概念以及系統架構也有詳細的介紹。並且提供了一系統模型用來分析系統穩定度以及動態行為。此時脈產生器佔用了0.09 mm2之晶片面積，實現在0.18

關鍵字

延遲鎖定迴路；時脈產生；相位偏差；電容倍化；時脈抖動

並列摘要

The delay-locked loop(DLL) is widely used in many aspects, such as the generation of multiphase clocks or clock generator. In this dissertation, a fully integrated multiplying DLL and a distributed DLL are covered. A general impedance converter (GIC) is used in multiplying DLL to greatly reduce the chip area. To solve the problem brought by the loss in a GIC, an adaptive current tuning technique is proposed. The multiphase clocks are typically suffered from the random mismatches with different devices. The distributed DLL is designed for the generation of multiphase clocks with good phase accuracy and low jitter, which requires no extra calibration circuits. The on-chip capacitance multiplication is typically realized by Miller effect, but the capacitance multiplication factor is limited due to device mismatches. A GIC is utilized to greatly multiply the on-chip capacitor by 2000 times. The nonidealities in a GIC are analyzed. To solve the problem, an adaptive current tuning technique is proposed to deal with the loss in a GIC. The concept and the architecture of the clock generator with adaptive current tuning are presented. A system model for the analysis of the stability and the dynamic behavior is provided. The clock generator occupies an active area of 0.09 mm2 in a 0.18-

並列關鍵字

delay-locked loop ； clock generation ； phase mismatch ； capacitance multiplication ； clock jitter

參考文獻

[1] B. Razavi, "RF Microelectronics," 1st Ed., Prentice Hall, 1998.

[2] B. Razavi, "Design of Integrated Circuits for Optical Communications," 1st Ed., Mc-Graw Hill, 2003.

[4] T.-C. Lee, and K.-J. Hsiao, "The Design and Analysis of a DLL-Based Frequency Synthesizer for UWB Application," IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 1245-1252, Jun. 2006.

[5] B. Razavi, "Design of Analog CMOS Integrated Circuits," 1st Ed., McGraw-Hill, 2001.

[6] A. A. Abidi, “High-Frequency Noise Measurements of FETs with Small Dimensions,” IEEE Trans. Electron Devices, vol. 33, pp. 1801-1805, Nov., 1986.

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高效能延遲鎖定迴路的設計與應用

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