並列摘要
This thesis presents a novel diagnosis technique for multiple defects. This technique proposes a simple heuristic to partition the failures log so that hard-to-detect defects and easy-to-detect defects are likely to be separated. Hopefully, each defect can be diagnosed individually. This technique requires only commercial diagnosis software with a simple add-on tool. No customized diagnosis software is needed. Simulations on benchmark circuits demonstrated the effectiveness of the proposed technique. Real silicon experiments on a real industrial product have been verified by physical failure analysis.
參考文獻
[Bartenstein 01] T. Bartenstein, D. Heaberlin, L. Huisman, and D. Sliwinski, “Diagnosing Combinational Logic Designs Using the Single Location At-a-time (SLAT) Paradigm,” in Proc. of Int’l Test Conf., pp. 287-296, 2001.
[ITRS 11] Semiconductor Industry Association, “International Technology Roadmap for Semiconductors” 2011.
[Chen 14] P.-J. Chen, C.-C. Che, J. C.-M. Li, S.-F. Kuo, P.-Y. Hsueh, C.-Y. Kuo, and J.-N. Lee, “Physical-aware Systematic Multiple Defect Diagnosis,” IET Computers & Digital Techniques (accepted Feb. 2014).
[Yu 10] X. Yu, and R. D. Blanton, “Diagnosis of Integrated Circuits With Multiple Defects of Arbitrary Characteristics,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 6, pp. 977-987, 2010.
[Huisman 04] L. M. Huisman, “Diagnosing arbitrary defects in logic designs using single location at a time (SLAT),” IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 1, pp. 91-101, 2004.