針對機率電路之高效率且低誤宰測試

High Efficiency and Low Overkill Testing for Probabilistic Circuits

李明庭(Ming-Ting Lee)

指導教授 ： 李建模

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2019年)

https://doi.org/10.6342/NTU201901586

摘要

機率電路是一種極低功耗電路設計的未來走向，機率電路可以在正確率以及功耗當中做出良好的取捨，尤其適合用在一些能容錯的應用像是影像處理以及機器學習。然而機率電路的行為模式比傳統電路來得更加複雜，因為前者在給定相同的輸入圖樣下，有可能會產生不同的輸出結果，我們需要重複很多次測試才能獲得一個輸出的機率分布來描述機率電路，在這篇論文當中，我們提出了一個測試方法特別針對具有機率行為的電路，我們使用了多變數假設檢定來減少測試圖樣的重複次數，我們同時也使用斷層測試來判斷一個接受測試電路的好壞藉此達成減少誤宰的情形，實驗結果顯示我們的總測試圖樣長度比過去技術平均少了82%的長度，我們的誤宰機率也比過去技術平均減少了99%。

關鍵字

機率電路 ； 測試圖樣壓縮

並列摘要

Probabilistic circuits are a potential solution for low power designs which trade off correctness for power consumption. Probabilistic circuits are especially suitable for error-tolerant applications such as video processing or machine learning. The behavior of probabilistic circuits is more complicated than deterministic circuits because the former produce different outputs given the same inputs. Quantum circuits are sols inherently probabilistic circuits. When testing, we need to apply test patterns many times to obtain output distribution of probabilistic circuits. In this thesis, we propose a test flow targeting circuits with probabilistic behavior. When testing, we apply multivariate hypothesis testing to reduce pattern repetition. We also reduce overkill by tomographic testing to determine pass or fail of circuit under test (CUT). Experimental results show that our proposed technique can reduce pattern repetition by 82% and reduce overkill by 99% than a previous work.

並列關鍵字

Probabilistic Circuit ； Test Pattern Compression

參考文獻

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