多核心系統晶片之系統層級管理

System-Level Power management for MPSoC

黃教偉(Jiao-Wei Huang)

指導教授 ： 楊佳玲

國立臺灣大學/電機資訊學院/資訊工程學研究所/碩士(2010年)

https://doi.org/10.6342/NTU.2010.01931

摘要

半導體技術的進步導致漏電流迅速的增加，漏電流將會成為多核心系統晶片平台的瓶頸，因此當處理單元(processing element)處於閒置狀態時，我們想藉由電源閘控(power gating)來減少漏電流的消耗。電源閘控是目前最有效減少漏電流的方法之一，但是如果無法精準的使用電源閘控，反而會造成效能以及能量額外的消耗。許多研究已經提出如何使用歷史的資訊來預測未來處理單元的閒置時間以便做電源閘控。這些研究通常會先觀察處理單元的使用狀況，當偵測到的
閒置時間超過一個界線，便做關閉的動作。這些方法主要有三個缺點：(1)這些研究主要會利用幾個週期(cycle)來偵測處理單元是否處於閒置狀態，而這些週期無法用來省處理單元的電，導致有些可以被省的電卻浪費了。(2)這些研究並沒有一個提早喚醒處理單元的機制，因為他們並不知道閒置的時間會何時結束。(3)這些研究僅僅只是利用過去幾個閒置的週期來預測未來的閒置週期，這種閒置時間預測基本上很不精準。我們希望可以利用更多匯流排(bus)上的資訊來更精準的預測處理單元的閒置時間。
在這篇論文中，我們設計了一個電源管理機制，利用性能監測單元和功率控制單元優化能源消耗和性能損失。性能監測單元用來收集匯流排上的訊息以及預測處理單元的閒置時間，然後功率控制單元再利用性能監測單元提供的閒置時間資訊來控制每個處理單元的電源模式。我們相我們的電源管理機制實作在Coware Platform Architect平台上，實驗結果顯示我們的機制可達45%的省電效果，而且只令性能下降4%左右。

關鍵字

系統層級 ； 電源管理電源閘控 ； 多核心系統晶片 ； 性能監測單元

並列摘要

Semiconductor technology scaling down results in rapidly increasing of leakage power consumption. Leakage consumption would be the bottleneck on MPSoC. Therefore, we want to reduce leakage consumption with power gating when the processing element is idle. Power gating is the most effective way to reduce leakage. However, power gating would cause performance overhead and energy penalty if badly controlled. Many works have been proposed to predict idle time for power gating by using history information. These works usually observe the state of the processing element and turn it off after seeing a streak of idle cycles. These kinds of methods have three disadvantages. The first disadvantage is that these works waste several cycles to determinate whether the processing elements enter low power mode or not. It decreases the power saving potential. The second disadvantage is that these works don’t wake up processing elements early to reduce the wake up penalty. The third disadvantage is that they use the history idle cycles to predict future idle cycles. However, this history based prediction is very
inaccurate in MPSoCs.
In this thesis, we design a power management policy to optimize leakage energy consumption and performance penalty by using performance monitor unit(PMU) and power control unit(PCU). In the system, PMU first collects the bus information and predicts the idle time of each processing element. After predicting the idle time, PCU controls power mode of each processing element with predicted idle time provided by PMU. We implement the power management policy on Coware Platform Architect. The experimental results
show that our management policy could achieve 38% leakage power saving while the performance slowdown is about 4%.

並列關鍵字

System level ； power management ； power gating ； MPSoC ； Performance monitor unit

參考文獻

[1] N. Agarwal and N. J. Dimopoulos. Automated power gating of registers

the 7th international conference on Embedded computer systems, pages

[2] R. A. Bergamaschi and Y. W. Jiang. State-based power analysis for

USA, 2003. IEEE Computer Society.

[4] Y. Cho, Y. Kim, S. Park, and N. Chang. System-level power estima-