應用於生醫系統之類比低功率信號處理器

超大型積體電路技術使生物醫學儀器開了另一扇門，帶動了生物醫學微機電系統(Bio-MEMS)及無線網路等二領域技術的興起。利用可植入人體的生物醫學系統記錄神經刺激和生理信號，再用無線電路傳送信號的個人生物醫學遙控測試系統已變成一項新研究領域。在此系統中，如何減少置於人體中電路的能量消耗，延長電池壽命，並避免電路功率消耗使溫度上升而對神經或是器官造成傷害，是主要的研究重點。針對此研究重點，本論文將提出消除接收器中混波器產生的直流偏移電壓架構，並設計其中的的低功率逐步逼近式類比數位轉換器(SAR ADC)與降頻濾波器電路。　　本論文所提出的十位元的類比數位轉換器是以省電電容陣列和分裂式比較器的架構來達到低功率操作的目的。比起傳統的電容陣列架構，此電容陣列架構可以降低68%的能量消耗。而本論文的分裂式比較器採用兩種不同增益的比較路徑，適當的選取其一路徑且關閉另一，達到省電的操作。此類比數位轉換器採用0.18μm CMOS的製程，在電壓為1伏特下，500KS/s的取樣頻率下所量到的信號噪音和失真比(SNDR)為58.4 dB，消耗功率為42μW。　　論文後半部份提出一個為了監測心電圖可攜帶系統的降頻濾波器設計。降頻濾波器功能上分為兩個部份，前級用來過濾雜訊後降頻的心電圖信號，後級是用來取出因為本地振盪器洩漏造成的直流偏移電壓，來跟原來的信號相減，得到一個適當的信號輸入給類比數位轉換器而不超過它的輸入電壓範圍。本設計並針對儲存的需求及每秒用到多少乘法器，來選擇最有效率的降頻比率。最後，透過Altera Stradix EP1S80 FPGA板的實作，以Tektronix TLA 715 邏輯分析儀，驗證此降頻濾波器功能之正確性。

關鍵字

類比數位轉換器；降頻濾波器

並列摘要

The application of VLSI technology in bio-medical instrumentation enables the emerging of the bio-MEMS and wireless technologies. By combining these technologies, personal remote sensing has become a popular research area. It applies an implantable bio-medical circuit for neural stimulation and uses RF signal to transmit recorded physiological signals. In such implanted bio-medical circuits, low power operation is very important because the heat spread caused by the implanted circuit will increase local temperature which may damage organs and neurons. This thesis presents a signal processor with area-efficient DC offset cancellation. For this processor, this work designs the building blocks of a low power 10-bit successive-approximation-register analog-to-digital converter (SAR ADC) and a low power decimation filter for bio-medical applications. In the 10-bit SAR ADC, an energy-saving capacitor array and a splitting comparator architecture is proposed to achieve low power consumption. The average switching energy of the capacitor array can be reduced by 68% compared to a conventional architecture. The splitting comparator consists of two gain paths, through which power saving for an A/D conversion is achieved by selecting the appropriate comparison path and disabling the unused path. The measured signal-to-noise-and-distortion ratio of the ADC is 58.4 dB at 500KS/s sampling rate with power consumption of 42μW from a 1-V supply. The ADC is fabricated in a 0.18-μm CMOS technology. A low-power decimation filter for portable electrocardiogram (ECG) monitoring applications is also presented. This decimation filter consists of two parts: front-end and back-end. The font-end filters noise to regain ECG signal while the back-end computes the direct current (DC) offset caused by the local oscillator (LO) leakage and subtracts it from the input. This makes the ECG signal stays within the allowable ADC input range. In addition, selecting the right decimation factors gives the most efficient design in terms of storage requirements and the number of multiplications per second (MPS). Finally, the functionality of the decimation filter is tested and verified with an Altera Stradix EP1S80 FPGA board and Tektronix TLA 715.

並列關鍵字

SAR ADC ； Decimation filter

參考文獻

[1.1] C. –H. Chen, et al., “A Wireless Bio-MEMS Sensor for C-Reactive Protein Detection Based on Nanomechanics,” ISSCC Dig. Tech. Papers, pp. 376-377, Feb 2006.

[1.2] R. Fensli, E. Gunnarson, and T. Gndersen, “A wearable ECG-recording system for continuous arrhythmia monitoring in a wireless tele-home-care situation,” In Preceedings of the IEEE International Symposium on Computer-Based medical Systems (CBMS), pp. 407-412, June 2005.

[2.1] S. Mortezapour and E. Lee, “A 1-V 8-bit successive approximation ADC in standard CMOS process,” IEEE J. Solid-State Circuit, vol. 35, no. 4, pp.642-646, Apr. 2000.

[2.2] J. Sauerbrey, D. Schmitt-Landsiedel, and R. Thewes, “A 0.5-V 1-μW successive approximation ADC,” IEEE J. Solid –State Circuits, vol. 38, no. 7, pp. 1261-1265, July 2003.

[2.3] M. Scott, B. Boser, and K. Pister, “An ultra low-energy ADC for smart dust,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1123-1129, July 2003.

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應用於生醫系統之類比低功率信號處理器

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