目錄式快取協定晶片內網路的流量改進

Use Banked Directory to Reduce Coherent Traffic in Network-on-Chip

蔡一邨(I-Tsuen Tsai)

指導教授 ： 賴飛羆

國立臺灣大學/電機資訊學院/電機工程學研究所/碩士(2011年)

https://doi.org/10.6342/NTU.2011.10600

摘要

在晶片製程的持續進步下，單一矽晶片已可容納高達一億個以上的邏輯閘。為了充分使用這些電晶體，並強化每單位運算功耗的效率(giga flop per watt) ，通用型處理器(general-purpose CPU)相繼採用multi-core的設計，並走向many–core on single die以提供平行化的大量運算效能。而在晶片內部的資料傳輸上，目前作為主流的匯流排架構將無法負荷大量核心運算器間的資料傳輸需求。近年來有許多論文提出晶片網路架構以解決此方面的挑戰，將較於匯流排架構，晶片網路架構擁有模組化、更大的頻寬、以及良好的可延伸性等優點。

在現有的晶片網路設計中，實現快取同步功能的封包將會耗用大量的傳輸頻寬，因而減損了晶片網路的資料傳輸性能。在這篇論文中提出透過記憶體位址解碼，將封包廣播式快取一致性方法改良為點對點快取一致性方法，以縮減此類封包的數量，在少量的邏輯閘增加下提供現有晶片網路更大的資料傳輸頻寬。相對於廣播式快取一致性方法，本方法在商用資料庫之平行化運算上提昇了平均30%的資料傳輸量。

關鍵字

晶片網路 ； 快取一致性協定 ； 系統晶片

並列摘要

We have ability to integrate more than ten billion transistors on Single silicon die nowadays by advantages of wafer manufacture technology. To fully utilize such high gate count and enhance the computing power efficiency (giga flop per watt), general purpose CPU now apply multi-core design, and towards many-core on single die for providing paralleled computing power. The mainstream BUS system design will not be able to fulfill the data transfer need between these huge amount CPU cores. Many researches introduce the Network-on-Chip (NoC) architecture to overcome this challenge, NoC contains many advantages such as modulized design, much higher data throughput, and well scalability.

It consumes large amount of data throughput to implement cache coherence function under current NoC architecture and therefore reduce the performance of Network-on-Chip. We introduced a method to reduce the cache coherence data amount by replacing broadcast-type cache coherence with peer-to-peer type cache coherence and distributed bank directory. This method improves 30% data throughput performance on average in commercial paralleled computing database compared to broadcast-type cache coherence method.

並列關鍵字

Network-on-Chip ； cache coherence ； System-on-Chip ； many-core

參考文獻

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