高效能與擁有可延展性嵌入式區塊編碼架構的JPEG 2000編解碼器

High Processing Efficiency JPEG 2000 Codec with Scalable Architecture for Embedded Block Coding

陳俊嘉(Chun-Chia Chen)

指導教授 ： 陳良基

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2006年)

https://doi.org/10.6342/NTU.2006.01182

摘要

JPEG 2000是相當優異的靜態影像壓縮標準。它不但有著高的壓縮倍率，更有著豐富的功能。與JPEG相比較，JPEG 2000的影像品質比JPEG好約1~4分貝，壓縮倍率更為JPEG的1.3~2.5倍之多。JPEG 2000的演算法相當有彈性，能夠以單一的演算法將各式各樣不同的影像種類以單一編碼流作編碼。JPEG 2000的演算法更能夠提供各式各樣有用的功能，例如影像大小的可延展性、信號雜訊比的可延展性、興趣區間的編碼、以及錯誤保護的功能。
對於JPEG 2000的應用，例如數位相機等等，JPEG 2000邊解碼器最重要的則是低價格考量。對於低價格考量的編解碼器而言，嵌入式區塊編碼的架構是最重要的。這是由於嵌入式區塊編碼區塊編碼時佔了系統52.3%的運算量，解碼時佔了系統61.0%的運算亮。並且，嵌入式區塊編碼架構佔了系統一半以上的矽面積。
在所有現有的嵌入式區塊編碼架構中，大約可以被分為兩個種類。位元層循序式嵌入式區塊編碼，以及係數層級平行式嵌入式區塊編碼。位元層循序式嵌入式區塊編碼是一個過低的設計，因為它的產出速度太低。係數層級平行式是一個過高的設計，因為它有嚴重的硬體浪費問題。為了將嵌入式區塊編碼最佳化，因而最佳化整個JPEG 2000邊解碼器的矽面積效率，我們在此本碩士論文當中，提出了擁有可延展性嵌入式區塊編碼架構的JPEG 2000邊解碼器。可延展性嵌入式區塊編碼架構除了可將矽面積效率最佳化之外，還可以對於不同的應用輕易延展到最佳的架構。
我們提出的編解碼器有以下三大特色。第一，嵌入式區塊編碼架構為完全可延展性的。第二，整個編解碼器的矽面積效率是最佳化的。第三，編解碼器的外部記憶體頻寬用了特殊技巧大量減低。
可延展性嵌入式區塊編碼架構可以輕易的針對不同的應用做延展。並且，可以將硬體資源與需要運算的資料作最佳的配合，達到最高的矽面積效率。可延展性嵌入式區塊編碼架構有著高產出速率與低價格的優勢。與傳統的係數層級平行式嵌入式區塊編碼架構做比較，可延展性嵌入式區塊編碼架構有著30.9%的產出速率增加，並且矽面積減少了50%以上。
我們提出的JPEG 2000編解碼器有著最佳的矽面積效率。在編解碼器當中有許多提出的技巧，去提升整體的矽面積效率，並且不太影響產出速率。這些技巧包含有，嵌入式區塊編碼的可延展性架構、發送器為基礎的算術編碼架構、狀態記憶轉換、以及編碼器與解碼器的高度硬體共用。實作結果證明，與過去已有的最好的編解碼器比較，我們的編解碼器有著49.3%的矽面積效率增長。
除了最佳化矽面積效率之外，本編解碼器的外部記憶體頻寬也大量減低。在編解碼器中，我們提出了資料流轉換以及嵌入式壓縮技巧，去最佳化外部畫面切割記憶體的輸出入，以及最小化外部畫面切割記憶體的存取。實驗結果證明，經過這些技巧之後，剩下的外部畫面切割記憶體的存取在編碼時只剩下55.1%，在解碼時只剩下42.4%。
為了驗證我們提出的嵌入式區塊編碼的設計方法，以及驗證我們提出的JPEG 2000邊解碼器的優越性，我們使用我們的理論來實作了一顆JPEG 2000邊解碼器。我們使用標準金氧半互補式場效電晶體的標準設計單元來實作晶片，並且使用台積電點一八微米製程下線。結果顯示，與過去最好的編解碼器相較，我們提出的編解碼器有著49.3%的矽面積效率改進，更有著112.3%的處理效率改進。

關鍵字

可延展性嵌入式區塊編碼 ； 資料流轉換 ； 嵌入式壓縮 ； 矽面積效率 ； 效能

並列摘要

JPEG 2000 is an excellent image coding standard. It has high coding gain and rich functionalities. Under the same bit-rate, image quality of JPEG 2000 is better than JPEG by 1~4 dB. The JPEG 2000 also has 1.3~2.5 times better coding gain than JPEG. Moreover, JPEG 2000 encodes different types of images with single code-stream by use of an unified algorithm. The JPEG 2000 algorithm also provides rich functionalities, such as spatial scalability, SNR scalability, region on interest coding, and error resilience.

For the applications of JPEG 2000, such as digital still camera, and so on, the cost efficiency design is a must. For the cost effective design, the architecture of EBC is very important. EBC occupies 52.3% of total computational complexity when encoding, and 61.0% when decoding. Moreover, EBC occupies over 50% of total chip area in a JPEG 2000 codec system.

In the previous works, all the architectures of the EBC can be classified into two categories, the bit-plane sequential EBC and the word-level parallel EBC. The bit-plane sequential EBC is an under-design because the throughput is limited. The word-level parallel EBC is an over-design because it has a serious hardware wasting problem. To optimize the EBC and maximize the silicon area efficiency, we proposed a high processing efficiency JPEG 2000 codec with scalable architecture for EBC. The scalable architecture for EBC can optimize the cost efficiency, and easily scalable for different applications.

The proposed codec has three features. First, the EBC architecture is fully scalable. Second, the silicon area efficiency of the codec is optimized. Third, the external memory bandwidth is highly reduced.

The scalable EBC can scale easily for different target applications. Moreover, the cost efficiency of EBC is optimized by matching the hardware resources to the total computation amount. The scalable EBC has high throughput and high area efficiency. Compared to the word-level EBC, the scalable EBC has a 30.9% better throughput, but 50% more area reduction.

The silicon area efficiency of the codec is optimized. There are many techniques to reduce the hardware cost under the same throughput. The proposed techniques includes the scalable architecture for EBC, the dispatcher based arithmetic coding, the state memory transformation, and the hardware sharing between encoder/decoder. The implementation result shows that, the proposed codec has a 49.3% improvement of area efficiency compared to the best codec of the previous works.

In addition to the improved area efficiency, the external memory bandwidth of the proposed codec is also highly reduced. We proposed the data-flow conversion, and the embedded compression to optimize the data-flow of the external tile memory I/O, and to minimize the external tile memory access. Experiments show that, the residual external bandwidth of tile memory access is only 55.1% when encoding, and only 42.4% when decoding.

In order to evaluate the proposed design methodology for EBC and the codec system, a prototype chip is implemented using Artisan standard CMOS cell library with TSMC 0.18um 1P6M technology. The result chip has a 49.3% area efficiency improvement, and a 112.3% processing efficiency improvement compared to the best codec of previous works.

並列關鍵字

Scalable Architecture for EBC ； Data-flow Conversion ； Embedded Compression ； Area Efficiency ； Processing Efficiency

參考文獻

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