非同步電路優化靜態性能分析的泛化與改進

現今的積體電路設計中，非同步電路的設計方法得到越來越多的重視。非同步電路的週期分析、死鎖(deadlock)驗證和優化在電路合成中都是非常重要的議題。以電路週期分析而言，線性規劃分析(linear programing based analysis)和靜態效能分析(static performance analysis)是現有做法中的兩個重要代表。線性規劃分析是高精度但低效率的，另外其分析結果是否符合實際電路的運作仍是未知。現今的靜態效能分析是高效率的，然而先前方法僅侷限於無環管線(acyclic pipeline)電路，並不能應用於有環管線(cyclic pipeline)電路的分析，且其精度還有待改進。此外，它在電路漸進式優化(incremental optimization)的應用上，效能分析必須被大量的重複使用，而先前的效能分析方法未針對漸進式優化的應用加以改良以至於非常沒有效率。在本論文中，我們展示了線性規劃分析的結果在某些情況下並不會在實際電路中發生，因而線性規劃分析的週期有可能低於實際值，我們因而解決了此一未知問題。此外，我們強化了靜態性能分析，使其能運用在有環管線電路而且適用在漸進式電路優化。另外，我們開發了一個應用於有環管線電路的死鎖驗證流程。我們進一步將這篇論文中提出的效能分析與死鎖驗證技術應用於電路的面積和效能優化。實驗結顯示我們的改進及泛化後的靜態效能分析總是得到精確的週期時間，其運算速度比線性規劃分析快了高達4000倍。此外，透過相對應的優化流程，電路面積平均可以減少19％，而電路效能也有顯著的改進。

關鍵字

非同步電路；靜態效能分析；線性規劃分析；效能優化；有環管線電路；死鎖

並列摘要

Asynchronous methodologies are gaining their presence in modern integrated circuit design. Cycle-time analysis, deadlock verification, and performance optimization are crucial to circuit synthesis. Among prior methods, linear programming-based analysis (LPA) and static performance analysis (SPA) are two representatives with high accuracy (but inefficient) and high efficiency (but inaccurate), respectively. However, the exactness of LPA remains unknown. Prior SPA can not be applied in cyclic circuits and its accuracy remains room for improvement. Moreover, SPA is not practical for incremental analysis in optimization iterations. In this thesis, we demonstrate the inexactness of LPA and enhance SPA to overcome its weakness. Also, we develop an efficient synthesis flow for deadlock verification in cyclic asynchronous pipelines and perform circuit optimization for area reduction and cycle-time improvement. Experimental results suggest our enhanced SPA almost always returns exact cycle-times while achieving up to 4000x speedup over LPA. Moreover, we conducted incremental logic transformation yielding an average of 19\% area reduction and iterative performance optimization with notable cycle time improvement.

並列關鍵字

asynchronous circuits ； static performance analysis ； linear programming-based analysis ； performance optimization ； cyclic pipeline ； deadlock

參考文獻

P. A. Beerel, G. D. Dimou, and A. M. Lines. Proteus: An ASIC Flow for GHz Asynchronous Designs. IEEE Design & Test of Computers, 28(5): 36-51, 2011.

D. Bufistov, J. Julvez, and J. Cortadella. Performance Optimization of Elastic Systems Using Buffer Resizing and Buffer Insertion. In Proc. Int'l Conf. on Computer-Aided Design (ICCAD), pp. 442-448, 2008.

C.-C. Chuang, Y.-H. Lai, and J.-H. R. Jiang. Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits. In Proc. Design Automation Conf. (DAC), pp. 192:1-192:6, 2014.

F. Chu and X.-L. Xie. Deadlock Analysis of Petri Nets Using Siphons and Mathematical Programming. IEEE Trans. Robotics and Automation, 13(6): pp. 793-804, 1997.

K. Fant and S. Brandt. Null convention logic: A complete and consistent logic for asynchronous digital circuit synthesis. In Proc. Int'l Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), pp. 261-273, 1996.

國際替代計量

非同步電路優化靜態性能分析的泛化與改進

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