具快速鎖定能力之全數位延遲鎖定迴路設計與分析

Design and Analysis of All-Digital Delay-Locked Loops with Fast-Locking Capability

陳右罡(You-Gang Chen)

指導教授 ： 曹恆偉

共同指導教授 ： 黃崇禧(Chorng-Sii Hwang)

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2012年)

https://doi.org/10.6342/NTU.2012.10731

摘要

隨著CMOS製程技術的發展和進步，高度整合的系統晶片在操作速度及效能上不斷地提昇，時脈誤差所造成時脈不同步現象也因操作速度的增加，而嚴重威脅系統運作的正確性，因此，IC內部與模組間的時脈同步課題，也相形更加的重要。在雙倍取樣的系統中，例如靜態記憶體和類比到數位轉換器，具有50%工作週期的訊號是非常重要的。因此，除了時脈訊號同步的問題外，時脈訊號之責任週期也需要被精準的控制，以提高電路操作之可靠度與正確性。
在本論文中，我們首先提出了同時實現時脈訊號同步與責任週期修正的去時脈誤差緩衝電路。藉由分析傳統使用兩組半延遲線的責任週期校正技術在製程漂移下導致延遲線不匹配所造成影響，並提出了三組延遲線與內差的方法來解決。為了達到快速鎖定，我們使用了一組循環式時間至數位轉換器在兩個參考時脈週期裡完成的責任週期的粗調。另外，我們提出了一個設定與重置訊號路徑相等的平衡式邊緣合成器來降低輸出訊號責任週期的失真。
另外，我們也實現了一大操作範圍下依然可以快速鎖定，且不會造成諧波鎖定的延遲鎖定迴路。本論文分析了除率對鎖定時間的影響，並提出了快速最大有效位元位置決定電路，使除率能維持最小值，並解決了諧波鎖定的問題。此外，可適性數位控制延遲線可根據操作頻率來調整延遲線的本質延遲，因而提高了電路的操作頻率。我們也提出可適性連續近似控制器，來搭配快速最大有效位元位置決定電路所取得的控制碼，依據不同操作速度調整二元搜尋法的長度，因而減少鎖定時間。
最後提出了與責任週期無關的快速鎖定之時脈訊號同步電路。我們使用了二級時脈誤差的補償方式：在第一級中，提出了一個具有省電設計的粗偏移補償電路，可利用單延遲線實現並且具備快速鎖定性能。為了減少鎖定時間與提高解析度，我們提出了非同步線性搜尋電路和差分延遲線的細偏移補償電路。
為了驗證以上所提出的三個全數位延遲鎖定迴路電路理論與架構，我們使用0.18微米的互補式金氧半導體製程來進行晶片設計與實現，測試結果均驗證其可行性並同時具有快速鎖定功能。

關鍵字

互補式金氧半導體 ； 系統晶片 ； 時脈誤差 ； 鎖相迴路 ； 延遲鎖定迴路 ； 雙倍取樣 ； 責任週期校正電路 ； 半延遲線 ； 循環式時間至數位轉換器 ； 諧波鎖定 ； 可適性連續近似控制器

並列摘要

With the evolution and the advancement of the complementary metal-oxide (CMOS) semiconductor process technologies, the performance and the operating frequency of the highly integrated system-on-a-chip (SoC) are raised higher and higher. The clock skew will cause the incorrect system operation seriously due to the asynchronous clocks. Thus, the aligning problem among IC modules and IPs in the SoC or system designs is becoming one of the bottlenecks for high performance systems. In double-sampling systems, like the DDR memory, the clock with the exact 50% duty cycle is very important. Consequently, the duty-cycle correction (DCC) plays an important role in such systems. In addition to the clock skew problem, the clock duty cycle also needs to be controlled accurately to improve the reliability and correctness of circuits
At first, a deskew buffer with DCC is proposed and realized. With the analysis of the impact on the duty cycle due to the delay line mismatch in conventional two half-delay line architecture, a new concept using three half-delay lines to alleviate the duty-cycle distortion is introduced to overcome the process variation. With the aid of a cyclic time-to-digital converter, the coarse locking time is reduced to only two cycles. A balanced-path edge combiner to produce a precise 50% output clock is also presented.
To obtain the wide-range, fast-locking, and harmonic-free functions, an all-digital delay-locked loop is proposed. A fast MSB decision circuit is designed to minimize the division ratio and to prevent harmonic-locking. Then, by using an adaptive digital-controlled delay line which can tune the intrinsic delay dynamically, the speed of DLL operation can be expanded. Furthermore, the adaptive SAR controller can change the binary search length with the operating frequency such that the locking time is reduced.
Finally, a duty-cycle independent fast-locking all-digital deskew buffer with an asynchronous linear search technique is presented. A coarse skew compensation circuit with a power-efficient design is proposed to achieve fast-locking. To reduce the fine compensation time with a higher resolution, the fine skew compensation circuit to realize the asynchronous linear search algorithm with the delay difference technique is designed to achieve fast-locking capability.
To verify the proposed circuit theories and architectures of the three all-digital DLLs described above, the test chips have been designed and fabricated using the CMOS 0.18μm process technology. The measured results of the chips prove the feasibility with the fast-locking capability

並列關鍵字

CMOS ； SoC ； clock skew ； PLL ； DLL ； double-edge trigger ； duty cycle corrector ； half-delay line ； cyclic time-to-digital converter ； wide range ； harmonic lock ； adaptive ； successive approximation register controller (SAR)

參考文獻

[1] Y. Moon, J. Choi, K. Lee, D.-K. Jeong and M.-K. Kim , “An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance,” IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 377-384, Mar. 2000.

[2] B.-G. Kim, L.-S. Kim, K.-I. Park, Y.-H. Jun and S.-I. Cho, “A DLL with jitter reduction techniques and quadrature phase generation for DRAM interfaces,” IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 1522-1530, May. 2009.

[4] H.-H. Chang and S.-I. Liu, “A wide-range and fast-locking all-digital cycle-controlled delay-locked loop,” IEEE J. Solid-State Circuits, vol. 40, no. 3, pp. 661-670, Mar. 2005.

[6] A. Hatakeyama, H. Mochizuki, T.Aikawa, and M. Takita, “A register-controlled symmetrical DLL for double-data-rate DRAM,” IEEE J. Solid-State Circuits, vol. 34, no. 4, pp. 565–568 Apr. 1999.

[7] J.-T. Kwak, C.-K. Kwon, K.-W. Kim, S.-H. Lee, and J.-S. Kih, “Low cost high performance register-controlled digital DLL for 1 Gbps 32 DDR SDRAM,” in IEEE Int. Symp. VLSI Circuits Dig. Tech. Papers, Aug 2003, pp. 283-284.