用於減輕掃描鍊位移時電壓降峰值的測試時域最佳化之平行化模擬技術

A Parallel Simulation Technique for Test Clock Domain optimization to Reduce Peak IR Drop During Scan

黃鈺筌(Yu-Chiuan Huang)

指導教授 ： 李建模

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2011年)

https://doi.org/10.6342/NTU.2011.02500

摘要

測試時域最佳化可以有效降低在掃描鍊移位時，所產生電源供應的電壓降峰值。但是，如何找到產生電壓降峰值的正反器依舊是困難的問題，因為要計算數以百萬的線性方程式。本篇論文提出了一個新的測試時域最佳化演算法，此技術可以直接調整產生電壓降峰值的正反器時域。在最佳化過程中，為了加速計算電壓降，本技術利用圖形處理器單元來實做平行化演算法。針對大型測試電路的實驗數據顯示，跟最佳化之前的電路相比，本技術將掃描鍊位移時的電壓降峰值平均降低百分之四十九。此外，本技術最佳化一個五十萬閘的測試電路只需要兩個小時以內。

關鍵字

電壓降峰值 ； 平行化電壓降模擬器 ； 測試時域最佳化 ； 可測試性設計

並列摘要

Test clock domain optimization has been shown to be an effective technique to reduce the power supply IR drop during scan chain shifting. However, finding the flip-flop of peak IR drop remains a difficult job because we need to solve millions of linear equations. This thesis presents a new TCDO algorithm that directly changes flip-flops where peak IR drop occurs. A massive parallel algorithm using graphic processor unit (GPU) is adopted to speed up the IR-drop calculation during optimization. The experimental data on large benchmark circuits show that peak IR drop values are reduced by 49% on the average compared with circuits before optimization. Our proposed technique quickly optimizes a half million gate design within 2 hours.

並列關鍵字

peak IR drop ； parallel IR-drop simulator ； test clock domain optimization ； design for testability

參考文獻

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