有機半導體應用於電晶體式記憶體 與可拉伸電子元件之製備與電子特性研究

Fabrication and Electrical Characteristics of Organic Semiconductors for Transistor-type Memory and Stretchable Electronic Devices

石健忠(Chien-Chung Shih)

指導教授 ： 陳文章

國立臺灣大學/工學院/化學工程學研究所/博士(2016年)

https://doi.org/10.6342/NTU201610325

摘要

隨著次世代消費性電子元件需求的快速增長，有機記憶體元件的進展受到廣泛的關注，除本身尺寸與材料結構多樣化等優勢外，有機記憶體尚須兼有溶液製程、高穿透度及良好的機械性質等特點。典型的有機記憶體為在場效應電晶體元件架構下，於半導體和介電層中加入一層額外的電荷儲存層，這當中以浮動閘極系統最為廣泛研究。目前浮動閘極的系統多以高真空濺鍍製備金奈米粒子作為電荷儲存點，然而此方式無法整合於溶液製程，除此之外，由於奈米金屬粒子的表面電漿共振效應，元件的光穿透度通常會因此而降低。另一方面，時至今日，有機記憶體元件僅具備可彎曲之特性，如應用於穿戴式電子裝置，尚須具備良好的拉伸性，本研究針對電晶體式記憶體，開發出溶液製程及高穿透度之記憶元件，並建立起可拉伸式電晶體的系統以期應用於記憶體，研究重點茲分述如下:
　　本文第一部分 (第二章)- 藉由再沉澱法製備尺寸約50-70 nm的聚芴系共軛高分子Polydioctylfluorene (PF) 和 poly(fluorene-alt-benzo[2,1,3]thiadiazole (PFBT) 之奈米粒子，並混摻入絕緣水溶性高分子Poly (methacrylic acid)(PMAA)做為奈米浮動閘極之電荷儲存層。研究發現共軛高分子奈米粒子具備良好的電子儲存特性，除此之外，我們可藉由調控奈米粒子的能階，使元件有較大的記憶窗口。在寫入/抹除的過程顯示出約35 V 的記憶窗口，以及大於10^4的開關電流比，記憶儲存時間可以達到10^4s。我們同時也做了PF和PS (polystyrene)的複合薄膜之電荷儲存層作為對照組，研究結果顯示將PF作為奈米粒子會相對於複合薄膜的方式具有更好的記憶儲存能力，原因在於奈米粒子可以被絕緣層有效的包覆，而複合薄膜系統則因高分子混摻形成微相分離，使PF區間與半導體層直接接觸，以致儲存電子的流失。
本文第二部分 (第三章)- 為了提升記憶體元件整體之穿透性，我們製備氧化鋅的奈米粒子作為奈米浮動閘極以儲存電荷。研究發現氧化鋅奈米粒子具備良好的電子儲存特性，為了進一步提升元件效能，利用具備電洞儲存特性的高分子 poly (9-(4-vinylphenyl) carbazole) (PVPK)和氧化鋅奈米粒子混摻形成複合薄膜，以達到同時捕捉電子及電洞的特性。在寫入/抹除的過程顯示出約60 V 的記憶窗口，以及大於10^4的開關電流比，記憶儲存時間可以達到10^4s。在可見光波長靠近500nm區段，整體元件的穿透度可高達90%。
本文第三部分 (第四章)-建立一個完整的全拉伸式有機場效電晶體系統，使其具備應用於記憶體的潛力。我們使用可交聯的氟化橡膠作為拉伸式電晶體的基材，並藉由不同的交聯密度分布使其產生皺摺，同時這個材料也做為介電層使用，共軛高分子 Poly(selenophene-alt-3,6-dithophene-2-yl-2,5-bis-(2-octyldodecyl)-2,5-dihydro-pyrrolo[3,4-c]pyrrole-1,4-dione) (PSeDPP) 則是作為半導體層。除此之外，高導電度的單壁碳管(SWCNT)以及Poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate)(PEDOT:PSS)/ (polyurethane) PU的複合材料則被選擇作為電極使用。研究發現具有皺褶表面的基材可減低共軛高分子在拉伸的過程受到的應力並將電晶體元件的每一層轉變為皺褶結構，同時由於氟化橡膠介電層在拉伸過程中提供良好的抗漏電能力，整體元件具有良好的拉伸特性。當拉伸比例為30%的狀態下，電晶體可重複拉伸超過2000次，並且仍可以保有(∼0.73 (cm^2 V^-1S^-1) 的電洞遷移率, 以及10^4 的電流開關比。未來此具備優良機械性質的電晶體將可作為電晶體式記憶體使用。
　　我們的研究針對有機電晶體式記憶體的製程改善，使其可應用於溶液製程，並具有高穿透度，同時我們也建立了一個完整的全拉伸式電晶體系統，以作為拉伸記憶體元件之使用。

關鍵字

電晶體式記憶體 ； 奈米浮動閘極 ； 共軛高分子奈米粒子 ； 氧化鋅奈米粒子 ； 全拉伸式電晶體

並列摘要

Recently, organic-based memory devices have received extensive scientific interest due to the rapid growth of the next-generation consumer electronic devices. Organic memory devices with the solution process, high transparency and well mechanical property are required, apart from their advantages such as flexibility, scalability, and material variety. A typical type of charge-trapping OFET memory is organic floating-gate memory. In this device, charges are stored in a metal nanoparticles called a floating gate, located within the insulating gate dielectric, and completely surrounded by insulator. In general, floating gate materials are gold nanoparticles (Au NPs), which required either high vacuum deposition or multiple processing steps to combine the charge-trapping sites with tunneling layer. Besides, the Au NPs possessed a strong absorption in the visible region due to their strong surface plasmon resonance effects. The devices with the Au NPs showed a lower transparency than that of the devices without the Au NPs. On the other hand, organic memory should be engineered to be durable enough to withstand high levels of strain for the wearable device applications. Therefore, efforts to develop stretchable types of transistor memory for advanced electronic circuits are important. The following summarize the important discovery of this thesis:
1. Conjugated Polymer Nanoparticles as Nano Floating Gate Electrets for High Performance Non-volatile Organic Transistor Memory Devices (chapter 2): A nano-floating gate material by using conjugated polymer nanoparticles (CPN) as the discrete trapping sites embedded in an insulating polymer was demonstrated. The nanoparticles of polyfluorene (PF) and poly(fluorene-alt-benzo[2,1,3]thiadiazole (PFBT) with average diameters of around 50-70 nm prepared from repcrecipitation method were used as a charge-trapping sites, while hydrophilic Poly (methacrylic acid) PMAA served as a matrix and a tunneling layer. The transistor memory device revealed a controllable threshold voltage shift, indicating effectively electron-trapping by the PF CPN. The memory device had a large memory window (35 V), retention time longer than 10^4 s with a high ON/OFF ratio of >10^4. In addition, the memory device performance using conjugated polymer nanoparticle NFG was much higher than that of the corresponding polymer blend thin films of PF/polystyrene (PS).
2. High Performance Transparent Transistor Memory Devices Using Nano-Floating Gate of Polymer/ZnO Nanocomposites (chapter 3) : The transparency of the device with metal NPs is restricted to 60~70% due to the light absorption in the visible region caused by the surface plasmon resonance effects of metal NPs. To address this issue, we demonstrated a novel NFGM using the blends of hole-trapping poly (9-(4-vinylphenyl) carbazole) (PVPK) and electron-trapping ZnO NPs as the charge storage element. The memory devices exhibited a remarkably programmable memory window up to 60 V during the program/erase operations, which was attributed to the trapping/detrapping of charge carriers in ZnO NPs/PVPK composite. Furthermore, the devices showed the long-term retention time (>10^4s) and high ON/OFF ratio of >10^4, indicating excellent electrical reliability and stability. Additionally, the fabricated transistor memory devices exhibited a relatively high transparency of 90% at the wavelength of 500 nm.
3. Elastomeric substrate with wrinkled surfaces for intrinsically stretchable organic thin film transistor (chapter 4): We employed the fluoroelastomer with the wrinkle surface as substrate for the intrinsically stretchable transistor, and this material is also used as the gate dielectric layer. Poly(selenophene-alt-3,6-dithophene-2-yl-2,5-bis-(2-octyldodecyl)-2,5-dihydro-pyrrolo[3,4-c]pyrrole-1,4-dione) (PSeDPP) with a high mobility as well as an air stability was selected to be the semiconducting layer. CNT and PU/PEDOT:PSS blend solution were used as the stretchable source/drain and gate electrode, respectively. The substrate could dissipate the applied strain on the semiconducting layer, and the transistor device was transformed to become the wrinkled structure after stretching, leading to a high endurance under strain. The device with high electrical mobility of ∼0.73 (cm^2 V^-1S^-1 and on-off ratio of 10^4 was stable over 2000 cycles of stretching under a 30% uniaxial strain.
Our study demonstrated new methods to fabricate solution processable organic transistor memory devices with a high performance. Besides, an intrinsically stretchable transistor with a high device durability at stretching was obtained, which could be applied to stretchable electronics.

並列關鍵字

transistor-type memory ； nano floating gate ； conjugated polymer nanoparticles ； zinc oxide nanoparticles ； stretchable transistor

參考文獻

[4] A. Tsumura, H. Koezuka, T. Ando, Appl. Phys. Lett. 1986, 49, 1210-1212.

[11] Y. Yang, J. Ouyang, L. Ma, R. J. H. Tseng, C. W. Chu, Adv. Funct. Mater. 2006, 16, 1001-1014.

[15] J.-S. Lee, J. Mater. Chem. 2011, 21, 14097-14112.

[16] T. Sekitani, T. Yokota, U. Zschieschang, H. Klauk, S. Bauer, K. Takeuchi, M. Takamiya, T. Sakurai, T. Someya, Science 2009, 326, 1516-1519.

[17] S.-T. Han, Y. Zhou, Q. D. Yang, L. Zhou, L.-B. Huang, Y. Yan, C.-S. Lee, V. A. L. Roy, ACS Nano 2014, 8, 1923-1931.