具製程、電壓與溫度背景校正之倍頻延遲鎖定迴路

A PVT-Tolerant MDLL with a Background Coarse-Frequency Selector and a Frequency Calibrator using a Delay-Calibrated SSPD

邱鈺凱(Yu-Kai CHIU)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2019年)

https://doi.org/10.6342/NTU201900154

摘要

本論文實現一具製程、溫度與電壓背景校正之倍頻延遲鎖定迴路，為了降低參考突波與相位抖動，本論文提出一具延遲校正之次取樣相位偵測器來校正頻率誤差，其中相位偵測器與電荷泵的相位雜訊不會被放大N2倍，為了增加迴路的頻率涵蓋與降低製程、溫度與電壓所造成的非理想效應，本論文也提出一背景執行之頻率選擇器，本論文已於台積電40奈米製程實踐與驗證，本電路輸出時脈為2.4GHz，其輸入參考頻率為150MHz，電路佈局面積為0.0135 mm2，於1V之工作電壓下，總功率消耗為5.2mW，量測之方均根抖動量為229fs，參考突波為-54.3dBc。

關鍵字

鎖相迴路 ； 倍頻延遲鎖定迴路 ； 頻率合成器

並列摘要

A multiplying delay-locked loop (MDLL) with a background coarse-frequency selector and a frequency calibrator is presented. To reduce the reference spur due to the frequency error, a frequency calibrator using a delay-calibrated SSPD is presented. The phase noise of the CP and the SSPD is not multiplied by N2. To cover a wide frequency variation, the background coarse-frequency selector is also presented. This MDLL is fabricated in 40-nm CMOS technology. The active area is 0.013mm2, and the power consumption is 5.2mW from a supply of 1V. It exhibits a root-mean-square jitter of 229fs at 2.4GHz output and the reference spur of -54.3dBc under a reference clock of 150MHz.

並列關鍵字

Phase-Locked Loop ； Multiplying Delay-Locked Loop ； Frequency Synthesizer

參考文獻

[1]Y. C. Huang and S. I. Liu, “A 2.4-GHz subharmonically injection-locked PLL with self-calibrated injection timing,” IEEE J. Solid-State Circuits, vol. 48, no. 11, pp. 417–428, Feb. 2013.

[2]A. Musa et al., “A compact, low-power and low-jitter dual-loop injection locked PLL using all-digital PVT calibration,” IEEE J. Solid-State Circuits, vol. 49, no. 1, pp. 50–60, Jan. 2014.

[3]S. Choi, S. Yoo, Y. Lim, and J. Choi, “A PVT-robust and low-jitter ring-VCO-based injection-locked clock multiplier with a continuous frequency-tracking loop using a replica-delay cell and a dual-edge phase detector,” IEEE J. Solid-State Circuits, vol. 51, no. 8, pp. 1878–1889, Aug. 2016.

[4]Y. Lee, H. Yoon, M. Kim, and J. Choi, “A PVT-robust −59-dBc reference spur and 450-fsRMS jitter injection-locked clock multiplier using a voltage-domain period-calibrating loop,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, pp. 238–239, June 2016.

[5]B. M. Helal, C. M. Hsu, K. Johnson, and M. H. Perrott, “A low jitter programmable clock multiplier based on a pulse injection-locked oscillator with a highly-digital tuning loop,” IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 1391–1400, May. 2009.