共晶錫鉛銲料電鍍於95/5高鉛銲料之擴散偶基本研究

高鉛銲料（High-lead solders）與共晶錫鉛銲料（Eutectic solders）接合而成的複合銲點已被廣泛應用做為以覆晶封裝（Flip-Chip package）技術應用之電子產品的銲點（Solder joint）結構。這些複合銲點在實際應用環境下，會受到許多外在因素影響，例如：必須承受晶片與基板間之熱膨脹係數值差異而導致的剪切應力，以及銲料與金屬墊層發生反應所形成的介金屬層，再加上銲點內的錫、鉛原子也會發生交互擴散，以上種種因素皆致使銲點微結構的演變相當多樣且造成其可靠度下降的機會大為提升。為了單純探討覆晶銲點中的複合銲料之間的界面反應行為，究竟對銲點微結構的發展提供何種程度之貢獻，並進一步分析其與上述其他外部因素造成銲點微結構演變之貢獻程度，以作為評估以此類銲點做為電子產品封裝時的使用壽命及可靠度之依據。本研究以電鍍製程將共晶錫鉛銲料（37Pb63Sn）電鍍於高鉛銲料（95Pb5Sn）板材之上獲得複合銲料擴散偶試片，經過迴銲反應使共晶錫鉛銲料融熔後再進行高溫儲存試驗（High Temperature Storage Tests, HTST），溫度為100、130、150、175℃，時間從100至2000小時不等，藉以探討兩銲料間彼此交互擴散反應。結果顯示複合擴散偶經過迴銲反應後，共晶錫鉛銲料電鍍層會融熔形成液態狀，並溶入部分的高鉛銲料，當迴銲溫度越高、時間越長、迴銲次數越多，則可溶入高鉛銲料的量也就隨之增加，則整體銲點就越趨向組成混合均勻的複合銲點。而將擴散偶經過長時間時效反應後，此銲料中的富鉛相與富錫相皆會持續發生粗化（Coarsening）現象，其驅動力是為降低整體系統之界面能。另外將部分未進行迴銲的複合銲料擴散偶試片，做為對照組，以比較迴銲反應對微觀組織的影響程度。結果顯示以電鍍製程獲得的鍍層微結構相當細緻，且存在於鍍層中的雜質會限制其晶粒成長，造成錫、鉛兩相於發生粗化過程時受到相當程度之抑制。

關鍵字

高鉛銲料；複合銲料；擴散偶；交互擴散；晶粒成長

並列摘要

Many of the flip-chip solder joints in electronics were composed of the high-lead solder bump, and the PbSn eutectic pre-solder. They would be affected by many environmental factors, such as thermal stress between chip and substrate due to the difference of coefficients of thermal expansion, intermetallic compounds formed in the interface between solders and metallic layers, and the interdiffusion of Pb and Sn atoms in solders. Hence, these factors would induce the microstructure of solder joints is various, thereby decreasing the reliability of solder joint. In order to understand the interfacial reaction behavior and clarify it playing what kinds of role in determining the reliability of solder joints, 95Pb5Sn/37Pb63Sn diffusion couples were used. In this study, we got the diffusion couples of composite solder by electroplating the 37Pb63Sn solder onto the 95Pb5Sn solder substrates. Then these diffusion couples were processed reflow process and high temperature storage tests at various temperature（100, 130, 150, and 175℃）for 100~2000 hrs to investigate the interdiffusion reaction. It is found that 37Pb63Sn solders could dissolve parts of high-lead solders while undergoing reflow process. The amount of high-lead solders is more if the experimental conditions are in higher temperature, longer time or more reflow times. Furthermore, the phenomenon of coarsening occurred in solders during aging process in order to reduce the interfacial energy. Besides, we use the non-reflow diffusion couples in the same conditions to compare the effects of reflow process. This result showed that the microstructure of the non-reflow diffusion couples is finer, and we deduced that many impurities in the 37Pb63Sn solder to impede the grain growth.

並列關鍵字

High lead solder ； Composite solder ； Diffusion couple ； Interdiffusion ； Grain growth

參考文獻

1. Michael Quirk and Julian Serda, Semiconductor Manufacturing Technology, 2003.

2. J. E. Morris, Workshop, The Design and Processing Technology of Electronic Packaging, 1997.

8. C. C. Chang, C. C. Lin, and C. R. Kao, unpublished.

10. S. Y. Hwang, J. W. Lee, and Z. H. Lee, Journal of Electronic Materials, vol.31, No.11, 2002.

12. S. Y. Tsai, C. R. Lee, G. J. Chiou, and J. G. Duh, Proceedings of 7th IEEE CPMT Conference on High Density Microsystem Design Packaging and Failure Analysis, June 27-30, 2005, Shanghai, China, p.99-104.

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共晶錫鉛銲料電鍍於95/5高鉛銲料之擴散偶基本研究

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