以場效可程式閘陣列實現肌電圖辨識系統

Implementation of EMG Pattern Recognition System in FPGA

林政廷(Cheng-Ting Lin)

指導教授 ： 郭德盛

共同指導教授 ： 康文柱 ； 林志隆

國立臺灣大學/電機資訊學院/電機工程學研究所/碩士(2005年)

https://doi.org/10.6342/NTU.2005.10184

摘要

臨床上若干動作障礙的病人，如截肢病人和脊椎損傷的病人，需要使用到一些輔助性的電子機械設備，如電動義肢、功能性電刺激器等等。如何有效的控制這些設備就成了重要的課題。在許多研究中，肌電圖訊號已經被廣泛使用來當作控制信號。因此本論文的主要目的為發展出一套建構在場效可程式閘陣列晶片中的肌電圖訊號辨識系統，研究中之核心演算法是依據本實驗室發展多年的肌電圖訊號辨識方法。
在本研究中的肌電圖訊號收集自身體兩側的胸鎖乳突肌和上斜方肌之間各貼一組主動式電極，辨識動作分為：頭轉左、頭轉右、右肩往上、左肩往上及兩肩往上等五種動作。以積分肌電圖偵測是否有動作產生，進而利用自相關函數法求出自動迴歸模型參數，再轉換為倒頻譜參數作為特徵值。這些特徵值以動態時間校正演算法進行判別。
硬體架構方面，主要包括三個部分：自相關函數、特徵擷取及分類器。由於同時要處理兩個通道的肌電訊號，將個別通道所計算得之特徵參數整合成一組用以辨識不同動作的特徵向量，為避免複製電路造成邏輯元件過多，增加生產成本，在考量肌電圖訊號辨識所需的辨識速度遠低於晶片的工作頻率下，我們採用時域多工(time-multiplexing)的方式，減少運算單元，達到小面積、低成本的需求。
自相關函數模組中，只使用一個乘加器來執行兩個通道的漢明窗及自相關函數之運算。特徵擷取演算包含除法運算，如果用軟體來實現需要一個微處理器，而且除法運算會佔用許多的時脈週期(clock cycles)，不適合我們的架構，因此在這個模組中加入一個減法和移位架構的除法器。而分類器的設計，首先觀察動態時間校正的演算過程，找出其運算上的規則，透過這些規則可以大量減少暫存器，並且求取特徵向量的距離上也共用一個減法器。最後將這些模組實現在Altera Stratix FPGA上，工作頻率大約為35MHz，使用了4379個邏輯單元。

關鍵字

肌電圖

並列摘要

The disabled people such as arm amputees or spinal cord injured patients usually need to use assistive devices like electric prosthesis or functional electrical stimulation system. It is an important topic to control these devices. EMG signal is one of the feasible control commands extensively investigated in many researches. An FPGA-based EMG recognition system is developed in this thesis. Most of core algorithms are derived from the previous researches of our laboratory.
Two sets of active electrode are bilaterally placed on the triangular region surrounded by the sternocleidomastoid, the upper trapezius, and the clavicle to collect surface EMG signals. Five motions of neck and shoulders are specified to provide possible control commands. The integrated EMG is computed to detect the onset of muscle contraction. The cepstral parameters derived from autoregressive coefficients are used as the recognition features. The autoregressive coefficients can be calculated by using the estimated autocorrelation lags in the Yule-walker equation. These features are then discriminated using the dynamic timing warping (DTW) method.
There are three parts in our hardware architecture including autocorrelation module, feature extraction module, and classifier module. The feature parameters from individual channel are concatenated to form a feature vector for classification. Two channels of EMG signal must be processed simultaneously. The data rate requirement of EMG signal processing is much lower than the clock rate of our chip design. To avoid rapid growth of logic units due to circuit duplication, we reduced the hardware functional units by time-multiplexing several operations such as multiplication and addition in algorithm. A design with small area and low cost can be achieved with the multiplexing controlled by a finite state machine (FSM). A single multiplication-and-accumulation (MAC) unit is shared to calculate Hamming window and autocorrelation functions of both two channels. There are several divisions used in Levinson-Durbin algorithm. A software solution usually needs a microprocessor to perform division; besides, it takes many clock cycles to complete a division, which is obviously not a good choice in our architecture. A sequential divider using subtract-and-shift algorithm is implemented in our design. After observing the operation flow of dynamic timing warping method, we establish some rules to reduce the amount of registers extensively. One subtractor is shared to calculate the distance between test and reference feature vectors. The final design is downloaded and verified on Altera Stratix FPGA. The simulation results show that the clock rate is 35MHz clock rate and the hardware requirement is 4379 logic elements.

並列關鍵字

EMG

參考文獻

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