使用區碼記憶之低密度同位元檢查碼編解碼器電路設計

Circuit Design for the LDPC Codec Using Interblock Memory

周泓甫(Hong-Fu Chou)

指導教授 ： 林茂昭

國立臺灣大學/電機資訊學院/電信工程學研究所/碩士(2006年)

https://doi.org/10.6342/NTU.2006.01499

摘要

根據參考文獻可知在編碼系統加上區塊記憶系統對於短編碼長度其錯誤更正能力具有大幅度改善,錯誤率效能都超越沒有區塊記憶系統。然而所需付出的代價是解碼複雜度以及速度增加。在此篇論文中，將實現LDPC 編碼解碼器以及具有延遲處理之LDPC 編解碼器，然後比較增加延遲處理器前後之硬體效能與錯誤更正能力差異。
在編碼器方面，我們根據Richardson 的高效率低複雜度之編碼器概念，然後Parhi 將此概念以位移循環方式之設計來建構編碼器。在這篇論文中，將此編碼器實現並且與以生成矩陣方式之編碼器比較效能與複雜度。在解碼器方面，我們是根據Parhi 所提出，使用Tanner graph 的概念以及部分平行式架構。
此外我們對區塊記憶解碼器之兩種設計， 即無遞迴式以及遞迴式之延遲處理解碼器架構都給予實現。在此篇論文中，描述此兩種硬體架構效能之優劣。

關鍵字

區塊記憶 ； 低密度同位元檢查碼 ； 電路設計

並列摘要

It has been shown that by properly introducing interblock memory to binary LDPC code, the decoded error rates can be significantly reduced for short code length.
However, the price is the increased decoding delay and decoding complexity. In this thesis, we conduct both the circuit design of LDPC codec and LDPC with interblock
memory codec. Then, we compare the performance of both coding scheme based on complexity and the error rate.
For the LDPC encoder, we consider two kinds of approaches. One was proposed by Richarson and was implemented by Parhi and the other is the generation matrix implemented by look up table. The decoder approach is implemented with partial
parallel architecture.
For the decoder of the LDPC code with interblock memory, it has been shown that there are two possible designs. One is the feedforward-only decoding and the other is the decoding with the feedback feature. In this thesis, we also compare the advantage and disadvantage of both designs based on the view of circuit application.

並列關鍵字

Interblock memory ； LDPC ； circuit design ； Implementation

參考文獻

Wei-Che Chang, Lin-Hung Chen, Hsie-Chia Chang, Chen-Yi Lee “A 480Mb/s

[1] T. Richardson and R. Urbanke, “Efficient encoding of low density parity-check

Feb. 2001.

[2] T. Zhang and K. K. Parhi, “Joint (3, k)-regular LDPC code and decoder/encoder

design,” to appear IEEE Transactions on Signal Processing, 2003.