適用於二維格狀多處理器晶片系統之可容錯晶片內網路架構

Fault-tolerant On-chip Network Architecture for 2D-mesh Based Chip Multiprocessor Systems

許展誠(Chan-cheng Hsu)

指導教授 ： 吳安宇

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2009年)

https://doi.org/10.6342/NTU.2009.02329

摘要

本論文中，為了提高晶片內網路之可容錯性並降低其在容錯情況下的效能損失，我們提出兩種晶片內網路架構：1) 20-path router with BIST/SD/FI (20PR)：內建自我測試/診斷/錯誤隔離電路的路由器設計。2) Surrounding Test Ring (STR)，一個由外部對晶片內網路進行測試與診斷的架構。它們除了具有自我測試/診斷(Built-in Self-Test/Self-Diagnosis)和錯誤隔離(Fault-Isolation)的功能以外，還可以使用路由器中未損壞的部份以降低容錯情況下的效能損失，如此的架構可以讓系統運用其特性重新分配工作到無錯誤的路徑上以維持系統的正常運作。
在我們的實驗中，20PR內建的自我測試診斷電路可以在117個週期時間中測試完畢，而STR可在144~376個週期中測試完畢。使用20PR的晶片內網路須付出15.17%的額外硬體成本，而使用STR的則需付出8.48%~13.3%。而在效能的方面，在我們的實驗中，與傳統將整個錯誤路由器關閉的作法，需重新配置的封包在20PR中降低了75.68%~83.29%，而在STR中降低了68.33%~79.31%。而系統的延遲在20PR中降低了7.25%~24.57%，在STR中則降低了4.86%~23.6%。實驗的結果呈現出來我們提出的可容錯晶片內網路架構可以有效的減少錯誤晶片內網路的效能損失。

關鍵字

晶片內網路 ； 容錯設計 ； 內建自我測試 ； 內建自我診斷

並列摘要

In this thesis, to improve fault-tolerance and reduce performance degradation in faulty on-chip networks, two on-chip network (OCN) architectures are proposed: 1) 20-path router (20PR), a router embedded with Built-in Self-Test/Self-Diagnosis (BIST/BISD) and Fault-Isolation (FI) circuits. 2) Surrounding Test Ring (STR), an external test architecture which externally perform test and diagnosis of the on-chip network. They embed BIST/SD and FI circuits that detect, locate, and isolate the impacts of the faulty FIFOs and MUXs in the faulty routers. Moreover, 20PR and STR apply undamaged datapaths in faulty routers to reduce performance degradation. The operation system can remap the tasks onto undamaged datapaths the proposed architectures found to maintain system function.
In our experiments, the BIST/SD of the 20PR can be executed in 117 constant test cycles and the STR can be executed in 144~376 test cycles. The overhead of the OCN using 20PRs increases 15.17%, while the OCNs with STRs increase 8.48%~13.3%. The experiments also show the performance improved over prior approaches which completely disable faulty routers. The remapped packets are reduced by 75.68%~83.29% for 20PR and 68.33%~79.31% for STR comparing to traditional approaches. The system latencies are also reduced by 7.25%~24.57% for 20PR and 4.86%~23.6% for STR comparing to traditional approaches. The experiment shows proposed fault-tolerant OCN architectures can perform graceful degradation in faulty mesh OCNs.

並列關鍵字

On-chip Network ； Fault-tolerant Design ； Built-in Self-test ； Built-in Self-diagnosis

參考文獻

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