摘要
隨著IC製程的快速演進，在相同的單位晶圓面積下，電晶體密度急遽地增加。相較於以往的產品，系統晶片(System-on-Chip)能夠整合更多樣的元件與更複雜的設計，以提供更豐富的功能與更強大的效能。面對此一高度集成之設計趨勢，晶片內元件間的連接架構也同時面臨著在軟硬體設計上更嚴苛的挑戰。在可預見的未來，傳統晶片所採用的匯流排(On-Chip Bus)架構，無論在功率消耗、性能要求、以及擴充彈性上，都即將難以滿足多核心(Many-Core)系統晶片內部元件間，因大量通訊所產生的複雜通訊需求。近年來，一種基於封包交換技術而實現的網路晶片(Network-on-Chip, NoC)傳輸架構逐漸地受到各研究單位與產業界的高度重視，然而其關鍵技術卻仍未瑧成熟。據此，本文提出一個新型的網路晶片路由器(NoC Router, NoCR)，其設計支援具流量感知能力之傳輸管理機制、高彈性選擇路徑之網路路由方法、與具雙向傳輸通道之容錯資料鏈結等功能，可分別相對於國際標準化組織（ISO）所定義之傳輸層、網路層、與資料鏈結層等功能。目前NoCR相容於Altera NIOS2 CPU，其功能並已通過FPGA系統板上的軟硬體協同驗證。實驗結果包含效能模擬與成本分析都明確地指出，相較於目前已知的設計方法，NoCR能更有效地增加傳輸效能，並提高運作可靠度；然而其實現成本包含晶片面積、功率消耗、與時序延遲卻都極其有限。最後希望本論文能對網路晶片的發展有所貢獻。
並列摘要
Network-on-Chip (NoC) is a promising on-chip communication infrastructure and is commonly considered as an aggressive long-term approach for on-chip communications in Multi-Processor System-on-Chip (MPSoC) and Chip Multi-Processor (CMP). An NoC Router (NoCR) that includes a network interface design and a 4-port router is proposed in this Dissertation. The NoCR design functions have been proven on an Altera FPGA development board with a NIOS2 CPU attached to the network interface. The flexible NoCR architecture enables fluidity-aware transport management, highly adaptive network routing, and bidirectional fault-tolerant data-link connection for on-chip communications. These functions respectively correspond to the Transport Layer, Network Layer, and Data-Link Layer, as defined in the ISO reference model. Tested with both synthetic traffic patterns as well as industry benchmark traffic patterns, significant performance enhancement and higher reliability have been observed when NoCR is compared to some state-of-the-art methods. Moreover, the implementation overheads analyzed by Synopsys Design Compiler in UMC 90nm technology are small in terms of chip area, power consumption, and logic latency. As a result, NoCR is an ideal on-chip interconnection solution for emerging many-core systems.