基於FPGA容量與頻寬限制之管線工作的加速方法

The Acceleration of Pipeline Workloads under the FPGA Area and Bandwidth Constraints

黃偉寧(Wei-Ning Huang)

指導教授 ： 郭大維

共同指導教授 ： 張哲維(Che-Wei Chang)

國立臺灣大學/電機資訊學院/資訊工程學研究所/碩士(2014年)

https://doi.org/10.6342/NTU.2014.02450

摘要

本文的動機來自於異質運算技術的進步以及現實應用中對於各種工作負載加速的強烈要求。對於執行在 FPGA 上的管線的工作,本文提出了一套系統化的方法來配置每個管線工作階段的硬體資源,並在 FPGA 記憶體頻寬的限制下,最小化所有管線工作階段中執行時間的最大值。對於這個問題,我們提出了一個演算法並證明其解法為最佳解,並在一個真實的平台上實做了此演算法。在我們的實驗中,以此方法實做在 FPGA 上的一個影像濾波器,其效能可以分別超越 CPU、 GPU 和基準FPGA 達 460%、 73%和 1030%。我們另外也對於擁有更多資源的 FPGA 裝置進行了深入的模擬,以證明此方法的擴充性。

關鍵字

異質運算系統 ； FPGA ； 管線工作 ； 加速器

並列摘要

This work is motivated by the advance of heterogeneous computing and the strong demands of workload acceleration in practice. By considering pipeline workloads over FPGA, this thesis explores a systematic methodology to configure the hardware instances of each pipeline stage such that the maximum of the execution time of each stage is minimized, where FPGA allocation with the memory bandwidth constraint is considered. For the target problem, an algorithm is proposed and proved being optimal, and a real implementation study is conducted. In the experimental study, an image filter FPGA implementation can outperform the CPU, GPU, and baseline FPGA solutions by 460%, 73%, and 1030%, respectively. Extensive simulations were also conducted with a large FPGA size to show the scalability of this work.

並列關鍵字

heterogeneous computing ； FPGA ； pipeline workload ； accelerator

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