準確且可實現的RC電路縮減

Accurate and Realizable RC Reduction

楊宜達(Yi-Ta Yang)

指導教授 ： 陳中平

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2022年)

https://doi.org/10.6342/NTU202201060

摘要

經由實驗數據發現TICER演算法中，不同種類節點以不同順序進行電路縮減會產生不同結果。本研究分別用計算以及實驗展示了同種節點間的順序不會造成顯著影響之餘，也進行估計值與實際值間誤差上限的分析，並且提出了對應於不同種類間順序的建議，相較於原演算法依照相鄰節點的數量排序，本研究提出的方法可以降低電路縮減所產生誤差的上限。最後於文末進行了實體設計電路以及隨機生成電路的電路縮減，兩者均顯示經由本研究縮減後的電路會有較相似於原始未縮減電路的特性。

關鍵字

電阻電容網絡簡化 ； 時序分析

並列摘要

The experimental results show that the reduction order would cause quite different outcomes when using the TICER algorithm. This thesis provides a suggestion on ordering the nodes which would make the upper boundary of the error smaller than reducing every node in the order of their connecting nodes. The experimental results of a real design circuit and a randomized circuit both demonstrate that circuits reduced by using the method provided in this work will be more similar to non-reduced circuits.

並列關鍵字

RC Reduction ； Timing Analysis

參考文獻

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