視訊解碼器架構之研究

A Study on Video Decoder Architecture

陳柏宏(Po-Hung Chen)

指導教授 ： 賴飛羆

國立臺灣大學/電機資訊學院/電機工程學研究所/博士(2007年)

https://doi.org/10.6342/NTU.2007.10290

摘要

最新的視訊編碼技術比較先前的視訊壓縮標準，它卓越的壓縮效率來自於很多新的特色，包括次像素畫面間預測、變動區塊尺寸的選擇及多重畫面參考、畫面內的預測和去除方塊效應。
然而它的整體計算複雜度也大大的增加，使得一個解碼器需要兩倍於MPEG-4解碼器或是MPEG-2解碼器的四倍的計算量。因此研究設計一個解碼硬體加速器是有其必要性。
本論文提出一個設計視訊解碼器架構的方法。一個有效率且有擴展性的巨區塊層級管線硬體架構被提出來支援視訊解碼功能。所提的解碼器架構包含多個解碼模組。由於其各基本功能的演算法都有複雜、依序性以及高度資料相依性的特性，不僅管線硬體架構，同時有效率的記憶體階層架構都是很需要的。因此本論文提出各解碼模組在巨區塊層級利用一區域緩衝記憶體來平行運作存在其中的資料與控制。
此外，除了整個解碼器架構的介面與設計，本論文提出了三個解碼模組架構設計的方法包含去方塊效應解碼模組、餘值重建解碼模組和運動補償解碼模組。每一個解碼模組的設計流程是一個由上到下的架構設計方法。透過視訊標準的規格分析，提出架構各功能的演算流程，並且分析設計各解碼模組所需的資料處理的效能與頻寬。然後將所需設計參數定義出來，此參數將用於決定設計架構所需的I/O以及資料流。

關鍵字

視訊解碼器 ； 架構

並列摘要

The high coding efficiency of the latest video coding technique outperforms the previous video coding standards from many new features, including sub pixel inter prediction with variable block size and multiple reference frames, intra prediction, and deblocking.
However, its overall computational complexity also increases greatly such that a decoder requires two times the computational power of a MPEG-4 decoder and four times of a MPEG-2 decoder. Hence, it is necessary to design a hardware accelerator for video decoder.
This dissertation presents the design methodology for video decoder. An efficient and scalable macroblock level pipeline architecture is proposed to support video decoding functions. The proposed decoder is composed of decoding modules. Due to the complex, sequential, and highly data dependent characteristics of all essential algorithms, not only the pipeline structure but also efficient memory hierarchy are required. The decoding modules process in parallel via accessing data and control in local memory buffer.
In addition to the interface and design of the whole decoding architecture, three decoding modules including deblocking module, residue reconstruction module and motion compensation module are presented. The design flow for each module is a top-down design methodology. Based on the analysis of the specification, the detailed architectural algorithm flow for each module is explored. And, the analysis of the requirements for the performance and bandwidth to design each module is calculated. Then, all required design parameters are defined to implement those modules. The information can be used to decide all required I/O, data flow to implement an architecture of a module.

並列關鍵字

Video decoder ； Architecture

參考文獻

[3] Atul Puria, Xuemin Chenb, Ajay Luthrac, "Video coding using the H.264/MPEG-4 AVC compression standard", SP:IC(19), No. 9, October 2004, pp. 793-849.

[8] Van de Waerdt, J.-W. and Vassiliadis, S., "Instruction set architecture enhancements for video processing," ASAP 2005, pages:146-153, 2005.

[10] To-Wei Chen, Yu-Wen Huang, Tung-Chien Chen, Yu-Han Chen, Chuan-Yung Tsai, and Liang-Gee Chen, "Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos," Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan, 2005.

[13] Iverson, V., McVeigh, J., Reese, B., "Real-Time H.264-AVC Codec on Intel Architectures," IEEE International Conference on Image Processing, Singapore, p.757-760, 2004.

[16] Wang Shu-hui, Lin Tao, Lin Zheng-hui, "Macroblock-level decoding and deblocking method and its pipeline implementation in H.264 decoder SOC design", Journal of Zhejiang University Science A, Vol.8 No.1 pages: 36-41, 2007.