針對三維積體電路中電源網路內缺陷穿矽通孔之微小延遲錯誤之測試向量產生

Test Generation of Path Delay Faults Induced by Defect in Power TSV

施啟仁(Chi-Jih Shih)

指導教授 ： 李建模

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2013年)

https://doi.org/10.6342/NTU.2013.02439

摘要

此論文主要針對三維積體電路內電源網路中的缺陷穿矽通孔(through silicon vias, TSV)所造成的路徑延遲錯誤(path delay fault, PDF)進行測試。此篇論文提出一個簡單的方法去分析缺陷對三維積體電路內電源網路的影響。我們發現在有很多穿矽通孔的情況下，開路缺陷發生在穿矽通孔時，並不會導致嚴重的電壓降。然而，當穿矽通孔的絕緣層上發生破洞時，即使在有很多穿矽通孔的情況下仍然必須被測試。此篇論文提出一套測試流程去測試缺陷穿矽通孔所造成的路徑延遲錯誤。我們使用一個18層，每一層具有7 x 7個核心的三維積體電路模型去證明我們的測試流程。在我們使用b18 和b19這兩種電路，所有可被測試的缺陷穿矽通孔所導致的路徑延遲錯誤都可以被偵測，且只需要約一百個測試圖樣。此外，此技術與先前技術的的最大不同點在於不需要額外的可測試性電路設計。

關鍵字

三維積體電路 ； 穿矽通孔 ； 路徑延遲錯誤 ； 穿矽通孔中的開路缺陷 ； 穿矽通孔之絕緣層上之破洞

並列摘要

This thesis presents a novel test generation technique for defective power TSV induced path delay faults in 3D IC. This paper provides a simple close-form analysis to show that, in a regular 3D power grid model, open defects in power TSV do not induce serious IR drop. However, leakage defects in power TSV should be tested, even though the number of power TSV is large. This thesis proposes a test generation flow to detect path delay faults induced by defective power TSV. The proposed technique is demonstrated on an 18-tier, 7 x 7 multi-core 3D IC model. In the experiment of b18 and b19 benchmark circuits, all detectable path delay faults induced by power TSV can be tested by around hundred test patterns. This technique requires no extra DfT hardware overhead.

並列關鍵字

Three-dimensional integrated circuit ； 3D IC ； Through silicon vias ； TSV ； open defect in TSV ； leakage defect in TSV

參考文獻

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