毫米波高位元率數位基頻接收機設計與實作

Design and Implementation of mm-Wave High Data Rate Digital Baseband Reveiver

黃子軒(Tzu-Hsuan Huang)

指導教授 ： 曹恆偉

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2012年)

https://doi.org/10.6342/NTU.2012.10788

摘要

在這個資訊爆炸的時代，無線通訊技術克服環境和佈線上的障礙，帶給人們通訊上的便利。然而目前大多數的無線通訊頻寬已相當擁擠，加上人們不斷追求更快的傳輸速度，使得屬於ISM頻帶的60GHz頻段為目前通訊發展的主流之一。60GHz頻段具有高達7GHz充裕的頻寬，加上毫米波視線傳播(line of sight)的特性，使其相當適用於高速短距離無線通訊。
然而數位系統在高速取樣下可用的運算時脈相當短暫，因此在硬體上要實現每秒百億位元以上的高速傳輸有一定的難度。本論文透過分析系統的雜訊和穩定性制定出最佳化參數，並採用平行化架構和管線技巧設計適用於高速傳輸的數位基頻接收機。
接收機設計為四路平行化架構並切三級管線，在AWGN通道並且最大載波頻率偏移為60GHz的100ppm、最大時脈偏移為傳送端時脈的100ppm的模擬環境下，定點數的位元錯誤率在E_b⁄N_0 等於10dB時達到3×〖10〗^(-5)，和浮點數位元錯誤率相差不到0.5dB。硬體實現用CIC提供的tsmc 90nm CMOS製成，後模擬的結果顯示系統最高操作頻率可達到312.5MHz，核心面積為0.77mm^2，利用率91.7%，功耗為18.6mW。

關鍵字

毫米波 ； 基頻 ； 高位元率 ； 架構 ； 接收機

並列摘要

In the era of information explosion, the wireless communication technology overcomes the obstacles on the environment and the wiring to bring the convenience of people’s communication. However, most of the communication bandwidth is already crowded, and people pursuit faster transmission speed, making the 60GHz band which belonging to ISM band is currently one of the main-stream of communication development. 60GHz band has wide bandwidth up to 7GHz, and millimeter-wave line-of-sight transmission characteristics make it quite suitable for high-speed, short-range wireless communication.
In the digital communication systems, the clock cycle used in high sampling rate system is quite short. As a result, it is difficult to achieve G-bit/sec data rate in hardware. This thesis proposes a parallel architecture design for a digital baseband receiver. Through pipeline techniques and analysis of the system noise and stability optimizing parameters to realize high-speed transmission.
The receiver adopts four-way parallel architecture and three stages pipeline. Simulation environment is AWGN channel with maximum carrier frequency offset 100ppm of 60GHz and maximum clock offset is 100ppm of transmitter clock. The BER of fixed point simulation is 3×〖10〗^(-5) at E_b⁄N_0 10db and the difference between floating simulation is less than 0.5 dB. Hardware simulation uses tsmc 90nm COMS process offered by CIC. The post layout simulation shows that the maximum operating frequency is 312.5 MHz, and core area is 0.77mm^2 with 91.7% utilization and 18.6mW power consumption.

並列關鍵字

mm-Wave ； baseband ； high data rate ； architecture, receiver.

參考文獻

[1] R. C. Daniels and R. W. Heath, "60 GHz wireless communications: emerging requirements and design recommendations," Vehicular Technology Magazine, IEEE, vol. 2, pp. 41-50, 2007.

[2] J. A. Howarth, A. P. Lauterbach, M. J. Boers, L. M. Davis, A. Parker, J. Harrison, et al., "60GHz Radios: Enabling Next-Generation Wireless Applications," in TENCON 2005 2005 IEEE Region 10, 2005, pp. 1-6.

[5] J. Zhang, N. Wu, J. Kuang, and H. Wang, "High speed all digital symbol timing recovery based on FPGA," in Wireless Communications, Networking and Mobile Computing, 2005. Proceedings. 2005 International Conference on, 2005, pp. 1402-1405.

[6] L. Zhiwei, P. Xiaoming, and F. Chin, "Joint Carrier Frequency Offset and Channel Estimation for OFDM Based Gigabit Wireless Communication System with Low Precision ADC," in Vehicular Technology Conference (VTC Fall), 2011 IEEE, 2011, pp. 1-5.

[7] P. Gianni, H. S. Carrer, G. Corral-Briones, and M. R. Hueda, "A novel low-latency parallel architecture for digital PLL with application to ultra-high speed carrier recovery systems," in Programmable Logic (SPL), 2011 VII Southern Conference on, 2011, pp. 31-36.