適用於40-Gb/s高速通訊系統之電路設計

隨著傳遞大量資料需求的升高，高速傳輸系統的發展也漸趨熱門。近年來，利用III-V半導體製程和SiGe BiCMOS製程，已有許多速度介於10~40 Gb/s之傳輸收發機實現。然而，利用CMOS製程來實現這樣的系統，仍舊是項挑戰。因此，本論文將描述CMOS製程在設計高速電路時主要面對的瓶頸，同時提出不同的電路技巧來克服。首先，本論文將介紹具備寬頻率調整範圍之0.18-µm CMOS 壓控振盪器。為了要在毫米波頻帶實現寬頻機制，提出利用切換傳輸線技巧的非勻稱性駐波振盪器。藉著傳輸線切換的方式，在40 GHz振盪頻率提供7.5 GHz的調整範圍，相位雜訊在1 MHz位移頻率時皆保持在-96 dBc/Hz以下。接著，本論文探討了注入鎖定式環型振盪器之鎖定範圍。為了要增加注入效率和除頻範圍，提出了多重注入的技巧，並在0.18-µm CMOS製程利用三級的寬頻環型振盪器作為理論驗證。量測結果顯示此除頻器在2:1和4:1除頻之可除範圍為13 – 25GHz和30 – 45 GHz。同時，多重注入技巧顯示除頻範圍相較於單端注入可有效地提升。最後，本論文將探討實現高速1:2解多工器。該電路之速度可藉由分散雜散電容之電流切換栓鎖器而有效提高。量測結果顯示本電路之最高速度可達20 Gb/s，在2-V工作電壓下，功率消耗為150 mW。

關鍵字

高速通訊系統；壓控振當器；除頻器；解多工器

並列摘要

As the demands for broadband communication continue to expand, the development of high-speed data link has attracted great attention. Recently, several transceivers ICs have been implemented in III-V compound semiconductor and SiGe BiCMOS process for data rate ranging from 10 to 40 Gb/s due to their superior device performance. However, it still remains a challenge for such transceivers to be integrated in a standard CMOS process. Consequently, this thesis describes the major limitations of the CMOS process for the individual building blocks, then presents several novel circuit techniques to reach the speed or bandwidth requirements for the system designs. First, a 40-GHz wideband VCO is demonstrated in a standard 0.18-um CMOS technology. In order to achieve wide tuning range at millimeter-wave frequencies, a non-uniform standing-wave VCO with switched-transmission line architecture is proposed. By switching the length of the transmission lines, a frequency tuning range of 7.5 GHz is achieved by the 40-GHz VCO while maintaining a phase noise better than -96 dBc/Hz at 1-MHz offset. Secondly, the locking ranges of the injection-locked ring oscillators are investigated. To improve the injection efficiency and the locking range for superharmonic frequency division, a multiple-injection technique is proposed. Using a 0.18-um CMOS process, a wideband frequency divider based on a three-stage ring oscillator is implemented for demonstration. With a tunable free-running frequency, the fabricated circuit provides 2:1 and 4:1 frequency division with a single-ended input signal ranging from 13 to 25 and 30 to 45 GHz, respectively. Compared with the case for a single-ended injection, the locking range of the frequency divider almost doubles when multiple input injections with optimum phases are utilized. The experimental results exhibit good agreement with the theoretical derivation and the circuit simulation. Finally, a high-speed 1:2 demultiplexer (DEMUX) implemented in a 0.18-um CMOS process is presented. By employing a distributed architecture for the current-mode-logic latches, a significant speed improvement is achieved in the proposed DEMUX circuit. Provided a 223-1 pseudo-random bit sequence from the pattern generator, the fabricated circuit operates at an input data rate up to 20 Gb/s. The fully integrated DEMUX consumes a dc power of 150 mW from a 2-V supply voltage.

並列關鍵字

High-speed communication system ； voltage-controlled oscillator ； frequency divider ； demultiplexer

參考文獻

Chapter 1

[1] B. Razavi, Design of Integrated Circuits for Optical Communications, McGRAW HILL, 2003.

[3] B. Razavi, “A 60-GHz CMOS receiver front-end,” IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 17-22, Jan. 2006.

[5] M. Tiebout, H.-D. Wohlmuth, W. Simbürger, “A 1V 51GHz fully-integrated VCO in 0.12µm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2002, pp. 300-301.

[6] A. P. van der Wel, S. L. J. Gierkink, R. C. Frye, V. Boccuzzi, and B. Nauta, “A robust 43-GHz VCO in CMOS for OC-768 SONET applications,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1159-1163, July 2004.

國際替代計量

適用於40-Gb/s高速通訊系統之電路設計

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