- 學位論文
使用可程式化邏輯陣列實現時域有限差分法
FPGA Implementation of Finite-Difference Time-Domain Algorithm
摘要
摘要 在本論文中, 我們使用 FPGA 來實現時域有限差分法 (FDTD)。FDTD 具有假設與近似少, 程式化容易,可分析時域變化等許多優點, 是一套功能非常強大的演算法。近來隨著電腦技術進步與奈米元件發展等因素, 在無線及光電領域越來越重要, 不過這方法需要龐大的計算時間與記憶體, 所以利用 FPGA 來縮短FDTD 的運算時間, 首先設計 FPGA 專注在 FDTD 的運算; 並透過時脈分配設計成管線化, 縮短指令的運算時間; 再搭配 Block RAM 雙埠及其高速的特性處理疊代運算的結果及暫存值的部份, 減少 FDTD 處理資料讀取的時間; 最後再加入平行運算到設計中; 綜合以上各項方法可以使速度明顯提升。 本文使用的FPGA是Xilinx的Spartan-3XC3S1500,數值表示方法是遵照IEEE-754 32 bit 的單精確度浮點數的規格, FDTD 的模擬系統是利用 SPI 介面將參數及初始值寫入, 並透過 VGA 介面將 FPGA 的運算結果讀出分析。 結果顯示, 即使在沒有平行處理的情況下, 將 FPGA 設計在 100 MHz 時的工作頻率, 在 1D FDTD 的結果中, 運算速度約是一般 2.01 GHz 個人電腦的30 倍; 在 2D FDTD 的結果大約是 15 倍。 當 FPGA 跟一般個人電腦工作在相同的頻率下, FPGA 的速度是一般個人電腦的數百倍。 最後在 1D FDTD 中加入兩組平行運算處理後,速度大約可以增加為兩倍。
並列摘要
In this thesis, we use field programmable gate array (FPGA) to implement finite-difference time-domain (FDTD).FDTD is a very powerful algorithm with advantages of minimum assumption and approximation, easy programming, and ability to analyze time domain variation. It has recently become more and more important in the field of wireless and optoelectronics due to the advancement of computer technology and the development of nanodevices. However, it requires a huge amount of computation time and memory.Thus, we use FPGA to reduce FDTD computation time.First, FPGA is designed to dedicate to FDTD calculation.Second, pipelining is achieved by means of clock arrangement to reduce computation time of instruction.Third, data access time is reduced by handling recursive calculation and temporary value with high-speed dual-port Block RAM.Finally, parallelism is added into design.Combining the strength above, the computation is greatly speeded up. The FPGA used is Xilinx Spartan-3 XC3S1500.The numerical representation complies with the IEEE-754 32 bit single-precision floating-point specification.In the FDTD simulation system, parameters and initial values are written via SPI interface,and the results computed by the FPGA are read out for analysis through the VGA interface. Our results show that the computation speed of 1D FDTD simulation is 30 times faster that of an ordinary 2.01 GHz personal computer when FPGA operated at clock rate of 100 MHz, and 15 times faster for 2D FDTD simulation even without parallelism.Equivalently, it can be hundreds times faster at the same clock rate.Finally, computation speed is doubled approximately by using two parallel computation units for 1D FDTD simulation.