匯流排與晶片系統之資料傳輸介面

在系統晶片(system-on-chip)設計中，矽智產之間皆利用匯流排互相溝通，隨著製程技術的進步，系統越來越複雜，單一晶片上的矽智產 (Intellectual Property)個數越來越多，使得匯流排在系統晶片發展上受到限制，在效能方面無法符合未來的系統需求；近幾年許多論文提出晶片網路(Networks-on-Chip)架構用以解決未來系統設計的挑戰，原因在於網路擁有較大的頻寬，規律性和模組化，改善了匯流排所面臨到的問題。晶片網路擁有二個主要的元件 : 路由器(router)和網路介面(Network Interface)。在利用較高的資料傳輸速率達到比匯流排更好的效能的前提之下，包括面積、功率消耗、傳輸延遲以及網路上的交通量將會是非常大的負擔，常會有壅塞或是熱點的形成，所以有大量論文和研究提出並改進這些問題；我們提出了一個新的架構:混合式晶片網路架構，基本上這是以晶片網路架構為基礎，但每個路由器所連接的並不是單一的處理單元，而是一個由AMBA匯流排連接多個矽智產的子系統，結合了兩種架構的優點，達到低延遲的架構。在這篇論文中，我們提出了一個簡單的網路介面設計不僅轉換匯流排訊號和網路封包資料而且幫助混合式晶片網路達到低延遲並解決熱點和經過節點數過多的問題。

關鍵字

晶片網路；晶片系統；網路介面；匯流排；低延遲

並列摘要

In system-on-chip design, each IP uses shared bus to communicate with the others. With the advance of the present time semiconductor technology and the increasing complexity of the system design, there are getting more and more IP cores. Because shared bus are nonscalable, they are limited in developing, and cannot reach the future system requirement in performance; In recent years, there are many papers proposing Networks-on-Chip (NoC) Architecture to overcome future systems design challenges, because of the higher bandwidth, regularity and modular in network. There are two major components: router and network interface in NoC architecture. Under satisfying the prerequisite of better performance than shared bus by using high data rate, including the traffic on network and the overhead of area, power and latency will be very large; it will often have congestion or hotspots in NoC. There are a lot of papers and researchers improving these problems; we address a new architecture: Hybrid Networks-on-Chip. It is based on NoC, and each switch connects a sub-system that is composed by linking many IPs on AMBA (Advanced Micro-controller Bus Architecture) rather than a single processing element. In this thesis, we propose a simple network interface design that not only transforms the AMBA signals and the packet data in network but helps hybrid architecture to achieve low latency and solve the problem of hop counts and hotspots.

並列關鍵字

Networks-on-Chip ； System-on-Chip ； Network Interface ； Bus ； low latency

參考文獻

[1] "AMBATM Specification Revision 2.0," May 13, 1999.

[2] L. Benini, L. Benini, and G. De Micheli, "Networks on chips: a new SoC paradigm," Computer, vol. 35, pp. 70-78, 2002.

[6] F. Karim, F. Karim, A. Nguyen, and S. Dey, "An interconnect architecture for networking systems on chips," Micro, IEEE, vol. 22, pp. 36-45, 2002.

[8] L. Ming, Z. Qing-An, and J. Wen-Ben, "DyXY - a proximity congestion-aware deadlock-free dynamic routing method for network on chip," in Design Automation Conference, 2006 43rd ACM/IEEE, 2006, pp. 849-852.

[13] S. Kumar, R. Holsmark and A. Johansson, "On connecting cores to packet switched on-chip networks: A case study with Microblaze Processor Cores," http://hem.hj.se/~hori/index-filer/Dokument/DDECS_2004.pdf.

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匯流排與晶片系統之資料傳輸介面

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