匯流排及晶片網路混合架構下之低延遲特定應用配置方法

隨著新技術的開發,允許我們將數百萬個電晶體整合入單一晶片.這些複雜的系統需要特殊的溝通資源去處理緊湊的設計需求.網路晶片(Networks-on-Chip)適合去處理這樣的需求,因為它提供了高擴充性、高重複使用性和高可靠性.二維網格(two–dimension mesh)是一種很受歡迎的網路晶片拓蹼.但是它的缺點是網路上傳輸距離比較遠所造成的延遲.在二維網格的中心常常形成熱點和壅塞.藉由將二維網格切割成幾個子系統並且以網路連接這些子系統,匯流排晶片網路混合系統可以減少二維網格傳輸時經過節點數過多的問題和其中心容易發生的壅塞問題.然而,要建置一些即時的應用在匯流排晶片網路混合系統時,有效的配置方法是必須被考慮的.在這篇論文中,我們提出了一個配置演算法在頻寬限制下可以將矽智產 (Intellectual Property)配置到匯流排晶片網路混合系統中,並且可以減少傳輸延遲和經過的節點數.

關鍵字

網路晶片；壅塞；延遲；匯流排晶片網路系統；配置演算法

並列摘要

New technologies allow the implementation of complex systems-on-chip (SoC) with hundreds of millions transistors integrated onto a single chip. These complex systems need special communication resources to cope with very tight design requirements. A NoC is suitable to deal with such requirements, since it provides high scalability, reusability and reliability. A popular network topology for Network-on-Chip implementations is the two-dimensional mesh. A disadvantage of the mesh topology is in its large communication radius. It often haves congestions or hotspots developed in the center of the mesh. By partitioning a two dimensional mesh into several sub-systems and connecting them using a network, Bus-NoC hybrid system can reduce the average number of hops for global traffic and the congestion in the center of the mesh. However, an efficient mapping strategy that can minimize the system communication delay of the system must be taken into account by the designer when regarding some real time application. In this theis, we present an algorithm that maps the cores onto a Bus-NoC hybrid system under the bandwidth constrains, and take advantage of locality to minimize the average communication delay and hop counts incurred by global traffic.

並列關鍵字

NoC ； Congestion ； Latency ； Bus-NoC hybrid system ； mapping algorithm

參考文獻

[1] Benini, L., L. Benini, and G. De Micheli, Networks on chips: a new SoC paradigm. Computer, 2002. 35(1): p. 70-78.

[2] Kumar, S., et al. A network on chip architecture and design methodology. in IEEE Computer Society Annual Symposium on VLSI 2002.

[4] Pande, P.P., et al. Design of a switch for network on chip applications. in Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on. 2003.

[5] Karim, F., et al., An interconnect architecture for networking systems on chips. Micro, IEEE, 2002. 22(5): p. 36-45.

[7] Ge-Ming, C., The odd-even turn model for adaptive routing. Parallel and Distributed Systems, IEEE Transactions on, 2000. 11(7): p. 729-738.

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匯流排及晶片網路混合架構下之低延遲特定應用配置方法

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