具有微縮化等效氧化層厚度高介電材料於鍺通道電晶體與金屬-氧化層-金屬電容之研究

在本篇論文中，著重在研究將高介電材料與其製程整合以介面處理以及微縮等效氧化層厚度之方式應用於(i)金屬-氧化層-金屬(金氧金)電容與(ii)鍺通道金屬-氧化層-半導體(金氧半)場效電晶體。由於傳統矽通道互補式金氧半元件尺度微縮面臨了物理限制，需使用其他新穎材料來提升元件效能以利製程微縮。高介電材料整合於高遷移率基板做為閘極堆疊層逐漸受到了重視，高介電材料/鍺通道的閘極堆疊層被期待能應用於十奈米節點之後。此外，高介電材料的採用在動態隨機存取記憶體元件已是必然的趨勢。在論文的第一部分，主要探討即場式水預處理於鉑電極對二氧化鉿金氧金電容的效應。在氫氧化的鉑表面上，有機金屬先驅物能有效與氫氧基鍵結，有利於二氧化鉿以原子層逐層組裝的方式進行沉積，亦抑制了以單斜晶為主要晶相的多晶化表現，並減少了二氧化鉿中的氧化層缺陷，呈現較佳的二次電壓係數為499 ppm/V2，亦能降低二氧化鉿表面的粗糙度，改善漏電流至4.8×10-8 A/cm2。進而將二氧化鉿導入至二氧化鋯氧化層中，以穩定其四方晶相。預水處理的效應影響了二氧化鉿鋯薄膜中的結晶成分比例，在120循環預水處理過鉑電極上的二氧化鉿鋯薄膜，其四方晶對單斜晶的比例較高，具有介電常數為34與等效氧化層厚度為1.6奈米，二次電壓係數因薄膜中缺陷的減少可降低至567 ppm/V2。在二氧化鋯金氧金電容上，進一步可達到微縮等效氧化層厚度至1.3奈米與二次電壓係數為424 ppm/V2與小於1μA/cm2的漏電流密度。在論文的第二部分，在氨氣/氫氣混合氣以遠控電漿方式於二氧化鍺/鍺基板處理過表面上，可形成無介面層並具有高介電常數為45±3的四方晶二氧化鋯作為閘極氧化層，製作出具有極小等效氧化層厚度為0.39奈米的氮化鈦/二氧化鋯/鍺的金氧半電容。我們發現到厚度約一奈米的二氧化鍺層在遠控電漿過程中被消耗，更可在後續退火處理後繼續變薄，以有利於氧化鍺脫附至二氧化鋯中。與其他高介電材料/鍺的閘極堆疊層相比，此結構具有四個數量級低的閘極漏電流密度。將此閘極結構應用於鍺通道場效電晶體製作上，在(111)晶面上可實現目前紀錄上最低的等效氧化層厚度為0.68奈米之N型場效電晶體，並具有電子遷移率為234 cm2/Vs。在(001)晶面上之場效電晶體可具有高開關電流比大於五個數量級以及低次臨界擺幅小於90 mV/dec。進一步分析電子遷移率與載子濃度關係，發現在中載子濃度區與高載子濃度區，遷移率將分別受遠端聲子散射與表面粗糙散射所控制。我們亦使用了機械式伸張應變來提升N型鍺通道電晶體的表現。最後一部分，在二氧化鋯上使用四氟化碳氣體作後閘極式電漿處理，發現二氧化鋯仍可以四方晶相形成。在等效氧化層厚度為0.4奈米的金氧半電容元件上，電性遲滯現象可從580 mV改善至200 mV，並且漏電流亦可降低，原因可歸於鋯-氟鍵結的形成，減少了二氧化鋯中的氧空缺缺陷數量。

關鍵字

二氧化鉿；二氧化鋯；原子層沉積；金氧金電容；鍺通道金氧半電晶體；表面處理；等效氧化層厚度微縮化

並列摘要

In this dissertation, high-permittivity (high-κ) materials and their process integration in terms of interface engineering and scaling technology for (i) Metal-Insulator-Metal Capacitors (MIMCAPs) and (ii) Ge channel MOSFETs are investigated. Since the traditional Si complementary metal-oxide-semiconductor (CMOS) scaling is approaching to its physical limits, introduction of performance boosters by alternative materials has become necessary to continue the scaling trend. Gate stack composed of a high-mobility channel with high-κ gate dielectric is attractive due to the enhancement of carrier mobility and device scaling capability. High-κ/Ge is expected to be utilized in sub-10 nm node and beyond. At the same time, high-κ materials are also of great interest for application in DRAM devices. In the first part of this dissertation, we investigate the effects of in situ H2O prepulse treatment on the surface of bottom Pt electrode for HfO2-based MIMCAPs. The hydroxylated Pt surface is able to facilitate the metalorganic precursor bonding with the -OH groups, favoring the layer-by-layer growth mechanism for HfO2 grown by atomic layer deposition (ALD) It also shows that the polycrystallization of HfO2 film with the predominant monoclinic phase can be suppressed. The better voltage-independent behavior of quadratic VCC α of 499 ppm/V2 in C-V curves of the MIMCAP can be described to the reduction of oxide traps in HfO2. Smaller roughness on HfO2 film surface produces the lower leakage current density of 4.8 × 10-8 A/cm2 at 1 V and at room temperature. Next, the HfO2 was introduced into ZrO2 dielectric layer to stabilize the tetragonal phase. The influence of H2O prepulse treatment on the phase components of HfZrO2 films shows that the intensity ratio of tetragonal to monoclinic phase could be enhanced by employing the 120-cycle H2O prepulse treatment, resulting in a higher κ value of 34, which also reduces the oxide traps, yielding the α value of 567 ppm/V2. Further scaled equivalent oxide thickness (EOT) down to 1.3 nm was demonstrated on the ZrO2 MIMCAP with an α value of 424 ppm/V2 and superior low gate leakage less than 1 μA/cm2. In the second part of this dissertation, the interfacial layer-free TiN/ZrO2/Ge metal-insulator-semiconductor capacitor (MISCAP) with a state-of-the-art EOT of 0.39 nm was fabricated by using tetragonal phase ZrO2 dielectric layer with κ value of 45±3 on NH3/H2 remote plasma treatment treated GeO2/Ge surface. The initial ~1 nm GeO2 layer is consumed during the remote plasma treatment, confirmed by x-ray photoelectron spectroscopy (XPS) and further thinned down by post-deposition annealing to trigger the GeO desorption into ZrO2. Superior low leakage property with four orders of magnitude reduction in low EOT region compared to other high-κ/Ge gate stacks was also demonstrated. By utilizing this gate stack on Ge MOSFETs, the Ge (111) nMOSFET with a record low EOT of 0.68 nm has an electron peak mobility of 234 cm2/Vs. Sub-1 nm EOT Ge (001) MOSFETs with high Ion/Ioff ratio > 105 and steep subthreshold swing < 90 mV/dec were demonstrated. The electron mobilities at intermediate ad high inversion carrier concentration are dominated by remote phonon scattering and surface roughness scattering, respectively. By applying the mechanical tensile strain, the performance of Ge nMOSFET can be further boosted. Finally, A post-gate CF4 plasma treatment can introduce fluorine incorporation into the tetragonal phase ZrO2 layer. The bulk traps in ZrO2 layer can be passivated by forming the Zr-F bonding feature, confirmed by the center-peaked fluorine energy dispersive x-ray spectrometry profile and XPS spectra. The electrical hysteresis was improved from 580 mV to 200 mV while the leakage current density was also reduced on the MISCAPs with the ultrathin EOT around 0.4 nm.

並列關鍵字

HfO2 ； ZrO2 ； ALD ； MIMCAPs ； Ge MOSFETs ； surface treatment ； EOT scaling

參考文獻

Chapter 1

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