- 學位論文
一個0.02mm2之鎖相迴路並採用次取樣與突波降低技術實現於90nm CMOS製程
A 0.02mm2 Sub-Sampling PLL with Spur Reduction Technique in 90nm CMOS Technology
摘要
本論文為一個小面積之鎖相迴路並採用次取樣與突波降低技術。現今中央處理器採用多個鎖相迴路分別給不同核心單元獨立使用，針對不同核心的工作狀態，動態地調整時脈頻率來減少功率消耗，同時隨著製程的演進，單位面積的製程成本持續成長，因此鎖相迴路的面積必須小型化，並且維持同樣的效能。傳統鎖相迴路中的迴路濾波器是由被動電容所組成，其占了晶片大部分的面積，因此把儲存電荷的電容改為儲存相位之電流控制震盪器可省下大量的面積。為了降低輸出的相位雜訊，本論文採用次取樣技術，當迴路鎖定頻率且參考訊號與除頻器輸出訊號相位差小於180度後，迴路會關閉增益較低的相位/頻率偵測器，改由較高增益的次取樣相位偵測器鎖定相位來降低其他電路所產生的雜訊，同時迴路也會關閉除頻器路徑，使其不會貢獻相位雜訊至系統。然而次取樣技術附帶的非理想效應會讓輸出訊號的參考突波增加，因此採用突波降低技術來減少次取樣電路所帶來的缺點。本晶片使用台積電90奈米互補式金氧半製程，主動區域面積約0.02mm2，在供應電源1.2V下輸出2 GHz頻率，參考突波達到-49.42 dBc，在偏移輸出頻率1MHz的相位雜訊為 -80.32 dBc/Hz，消耗 8.68mW功率。
並列摘要
The thesis implements a small area sub-sampling phase-locked loop(PLL) with spur reduction technique. Nowadays, CPUs adopt a number of PLLs for individual core in order to save the power consumption by dynamically adjusting the operation frequency. Along with the progress in process, the cost per unit area keeps increasing. Therefore, the area of PLL needs to be shrunk with the same performance.In the conventional PLL, the loop filter is composed of passive capacitor which occupies the most parts of chip area. As a result, the area of PLL can be saved by replacing the passive capacitor which stores or releases the charges with a current-controlled oscillator and a dummy oscillator which store the phase information. To reduce the output phase noise, the thesis adopts sub-sampling technique. As the output frequency is locked and the phase difference between reference and divider output is less than 180°, the frequency-locked loop is turned off and the sub-sampling phase detector with higher gain dedicates on phase locking. Meanwhile, the divider path is turned off so as to avoid the divider from contributing phase noise to system. However, the sub-sampling technique has three side effects and reference spur is raised up by those disadvantages. Hence, this thesis adopts spur reduction technique to alleviate those disadvantages from sub-sampling technique.This chip is fabricated in TSMC 90nm CMOS technology with an active area of 0.02mm^2 and 2GHz operation frequency. The reference spur is -49.42 dBc and phase noise is -80.32 dBc/Hz at 1MHz offset from carrier frequency under 1.2V power supply with 8.68mW power dissipation.