具快速鎖定與低抖動之非整數全數位鎖相迴路之設計與實作

Design and Implementation of a Fast-Locking, Low-Jitter Fractional-N All-digital Phase-Locked Loop

簡全佑(Chuan-Yu Chien)

指導教授 ： 楊家驤

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2018年)

https://doi.org/10.6342/NTU201800756

摘要

本論文提出了一應用於高速時脈的低抖動全數位鎖相迴路，可使用標準元件庫進行合成與實現，在不同製程之間容易進行轉換，大幅降低設計時間以及複雜度，適用於系統晶片之時脈產生。本論文提出之全數位鎖相迴路透過多個操作階段同時達到快速鎖定與低抖動特性，並且可藉由可程式化參數設定降低製程造成之效能變異。可程式化參數用於調整相位頻率偵測器、相位補償器、低通濾波器、以及數位控制振盪器，在初期階段使用倍率較大之迴路增益加速收斂速度，在後期階段則使用倍率較小之迴路增益降低抖動，並在追蹤頻率過程中將輸出頻率限制於可產生之頻率範圍，所採用之細部調整電路則可進一步減少穩定後之抖動。所設計之鎖相迴路以 40 nm 製程實現，核心面積為 0.08 mm2 ，在參考頻率為 100 MHz 時，輸出頻率範圍為 200 MHz 到 1 GHz 。平均約 1 μs 後可達到 7 ps 抖動的穩定時脈，操作穩定情況下之消耗的功耗為 0.8 mW ， FoM 為 -224.14 dB 。與過去文獻相比，所設計之晶片具有接近的抖動效能並消耗較低功率。

關鍵字

全數位鎖相迴路 ； 相位頻率偵測器 ； 系統單晶片 ； 三角積分調變器 ； 相位頻率補償器 ； 數位控制振盪器 ； 細調控制電流源 ； 固定的方均根週期抖動 ； 質量因數 ； 頻率控制數字

並列摘要

An efficient architecture for a low jitter all-digital phase-locked loop (ADPLL), suitable for high-speed digital clocking applications is presented. ADPLL is designed for standard cells and described using hardware description language (HDL) so that it can quickly and easily be ported to different processes. This reduction in design time and complexity makes it very suitable for use as a SoC digital clock. The proposed multi-stage architecture is conducive to fast locking and low jitter. In addition, programmable inputs attenuate process variation. The controller changes the phase frequency detector (PFD), phase feedback compensator (PCF), low-pass filter (LPF), and digital- controlled oscillator (DCO). At the initial stage, a large loop gain raises the speed for tracing. Later, small loop gain is used to attenuate jitter. Frequency is always lower than frequency control words (FCW) to avoid exceeding the oscillator limitation. Fine tuning architecture attenuates jitter after stability is achieved. The proposed ADPLL is implemented in a 40 nm CMOS process operating from 200 MHz to 1 GHz by a 100 MHz reference clock and has 7 ps with a 100 reference clock period while consuming a total of 0.8 mW with core area of 0.08 mm2. FoM is -224.14 dB which is low compared with other recent results.

並列關鍵字

All-digital phase-locked loop (ADPLL) ； phase frequency detector (PFD) ； system-on-chip (SoC) ； delta-sigma modulator (DSM) ； phase frequency compensator (PFC) ； digital-controlled oscillator (DCO) ； figure of merit (FoM) ； frequency control word (FCW)

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