基於可調整與雙射函數單元之高可測性重覆邏輯陣列

Testable Iterative Logic Arrays Based on Scalable and Bijective Cells

葉柏園(Po-Yuan Yeh)

指導教授 ： 郭斯彥

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2010年)

https://doi.org/10.6342/NTU.2010.02865

摘要

為了要得到一個可測之設計，一般而言必須將原始的電路設計適當地稍作修改。而不一樣的電路，其修改方式可大致區分為模組或位元上的修正來取得最佳之結果。但是傳統上，模組或位元上的修正通常分別會導致極大的測試向量數量（number of test pattern, NTP）或修正硬體數量（hardware overhead, HO）。為了克服這些問題，我們在本論文中提出一個新的測試技術，可以同時在測試向量數量與修正硬體之間取得較佳之平衡。
我們提出了新奇的可調整與雙射函數單元（scalable and bijective cell），讓這個新測試的技術可應用在重覆邏輯陣列電路架構上。所謂的可調整單元乃是指其由n個位元的小單元所組成，且具有硬體上與雙射函數上的可調整性。這些簡單的可調整單元將會建立起測試向量數量與修正硬體數量之間的數學上的關係，使得兩者都是n的函數。於是藉由調整n值，我們便可在測試向量數量與修正硬體數量之間獲得一最佳的平衡。 且所有使用可調整單元之重覆邏輯陣列電路架構都將成為常數可測（C-testable），也就是測試向量數量與重覆邏輯陣列的大小無關。
根據這新奇的可調整與雙射函數單元，我們可得到許多的可測電路，如乘累加器、N-tap 濾波器、矩陣乘法器以及座標轉換運算，且從所有的實驗數據中，與傳統之串接鏈測試方法（Scan-Chain method）相較，皆顯示新技術可獲得較佳之結果。以4x4的矩陣乘法器為例，新方法可得到(HO, NTP) = (4.87%, 74) ，且總共的測試時間只有串接測試方法的0.19%。以座標轉換運算電路來說，以可調整單元的可測設計與以組織過的測試序列的方法，其(HO, NTP) 分別也只有(5.37%, 74) 與(3.15%, 18)而已。
實驗顯示出新穎的可調整與雙射函數單元使得重覆邏輯陣列的測試架構有更好的優勢，與傳統的無可調整性重覆邏輯陣列的電路架構相較，有更可接受的測試向量數量與修正硬體數量。且在可調整與雙射函數單元幫助下，所有可測試之重覆邏輯陣列可以串接形成一更大的可測試之異質性（non-homogenous）的重覆邏輯陣列，這樣一來所有串接之異質性的重覆邏輯陣列不僅可以同時測試外，還可省下測試所需之輸出入腳位與內建自我測試電路的個數。此外，所提出的可調整與雙射函數單元也產生一個簡單且系統化的方法，來獲得最平衡的測試設計與可很簡易的取得類似電路架構之可調整單元。 本論文所提之方法，與現有之方法相較，更使得重覆邏輯陣列的測試架構為有實用性、系統化且對與現有之應用很有幫助。

關鍵字

常數測試 ； 測試設計 ； 座標轉換 ； 重覆邏輯陣列測試架構與可調性

並列摘要

In order to achieve testable designs, it is necessary to modify the original designs properly. For different applications, the modifications can be made at either module-level or bit-level circuits to achieve best results. In general, conventional test schemes at module-level or bit-level lead to large number of test patterns (NTP) or significant hardware overhead (HO), respectively. In order to circumvent these problems, we propose a novel test technique to achieve both acceptable NTP and HO by finding a balance between them in this paper.
We propose novel bijective and scalable cells to apply the technique on ILA-based (Iterative Logic Array) architectures. A scalable cell consists of n bit-level cells and has both hardware and bijective scalability. These simple scalable cells establish the relationship between HO and NTP, which is a function of n. By adjusting the value n, we can obtain an optimal balance between HO and NTP. The ILAs based on these scalable cells will still be C-testable i.e. testable with constant NTP independent of array size.
Based on the novel bijective and scalable cells, we have several C-testable designs for MAC (Multiplier-Accumulator), N-tap FIR (Finite Impulse Response) filter, matrix multiplication and CORDIC (COordinate Rotation DIgital Computer) design, where the experiments shows that it does achieve better results in comparison with traditional ATPG (Automatic Test Pattern Generation) method. For 4x4 matrix multiplication, the (HO, NTP) pairs with n = 2 are only about (4.87%, 74), and the total test time of the proposed method is only about 0.19% of that with the scan-chain method. For CORDIC design, the (HO, NTP) for n = 2 is (5.37%, 74) by scalable cells and the (HO, NTP) is only (3.15%, 18) by the reorganized test sequences.
It demonstrates that the novel scalable cells bring new advantage for ILA test schemes. It also results in both more reasonable NTP and HO at the same time compared with conventional ILA without scalability. With scalable and bijective cells, all the proposed ILA solutions can be connected together into a bigger non-homogeneous ILA for saving lots of test pins and BIST (Build-In Self Test) area. In addition, the proposed scalable cells induce a simple and systematic way to have balanced results and form new scalable cells. The proposed technique makes ILA-based DFT schemes more practical, systematic and useful for real and complicated applications than existing approaches.

並列關鍵字

C-testable ； Design-For-Testability (DFT) ； Iterative Logic Array (ILA) ； Logic Testing ； Scalability ； CORDIC (COordinate Rotation DIgital Computer)

參考文獻

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